Commit fade9c2c authored by Fuad Tabba's avatar Fuad Tabba Committed by Will Deacon
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arm64: Rename arm64-internal cache maintenance functions 



Although naming across the codebase isn't that consistent, it
tends to follow certain patterns. Moreover, the term "flush"
isn't defined in the Arm Architecture reference manual, and might
be interpreted to mean clean, invalidate, or both for a cache.

Rename arm64-internal functions to make the naming internally
consistent, as well as making it consistent with the Arm ARM, by
specifying whether it applies to the instruction, data, or both
caches, whether the operation is a clean, invalidate, or both.
Also specify which point the operation applies to, i.e., to the
point of unification (PoU), coherency (PoC), or persistence
(PoP).

This commit applies the following sed transformation to all files
under arch/arm64:

"s/\b__flush_cache_range\b/caches_clean_inval_pou_macro/g;"\
"s/\b__flush_icache_range\b/caches_clean_inval_pou/g;"\
"s/\binvalidate_icache_range\b/icache_inval_pou/g;"\
"s/\b__flush_dcache_area\b/dcache_clean_inval_poc/g;"\
"s/\b__inval_dcache_area\b/dcache_inval_poc/g;"\
"s/__clean_dcache_area_poc\b/dcache_clean_poc/g;"\
"s/\b__clean_dcache_area_pop\b/dcache_clean_pop/g;"\
"s/\b__clean_dcache_area_pou\b/dcache_clean_pou/g;"\
"s/\b__flush_cache_user_range\b/caches_clean_inval_user_pou/g;"\
"s/\b__flush_icache_all\b/icache_inval_all_pou/g;"

Note that __clean_dcache_area_poc is deliberately missing a word
boundary check at the beginning in order to match the efistub
symbols in image-vars.h.

Also note that, despite its name, __flush_icache_range operates
on both instruction and data caches. The name change here
reflects that.

No functional change intended.

Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
Signed-off-by: default avatarFuad Tabba <tabba@google.com>
Reviewed-by: default avatarArd Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20210524083001.2586635-19-tabba@google.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 393239be

arch/arm64/include/asm/arch_gicv3.h

+1 −1
Original line number Diff line number Diff line
@@ -125,7 +125,7 @@ static inline u32 gic_read_rpr(void) 
#define gic_write_lpir(v, c)		writeq_relaxed(v, c)



#define gic_flush_dcache_to_poc(a,l)	\

	__flush_dcache_area((unsigned long)(a), (unsigned long)(a)+(l))

	dcache_clean_inval_poc((unsigned long)(a), (unsigned long)(a)+(l))



#define gits_read_baser(c)		readq_relaxed(c)

#define gits_write_baser(v, c)		writeq_relaxed(v, c)

arch/arm64/include/asm/cacheflush.h

+18 −18
Original line number Diff line number Diff line
@@ -34,54 +34,54 @@ 
 *		- start  - virtual start address (inclusive)

 *		- end    - virtual end address (exclusive)

 *

 *	__flush_icache_range(start, end)

 *	caches_clean_inval_pou(start, end)

 *

 *		Ensure coherency between the I-cache and the D-cache region to

 *		the Point of Unification.

 *

 *	__flush_cache_user_range(start, end)

 *	caches_clean_inval_user_pou(start, end)

 *

 *		Ensure coherency between the I-cache and the D-cache region to

 *		the Point of Unification.

 *		Use only if the region might access user memory.

 *

 *	invalidate_icache_range(start, end)

 *	icache_inval_pou(start, end)

 *

 *		Invalidate I-cache region to the Point of Unification.

 *

 *	__flush_dcache_area(start, end)

 *	dcache_clean_inval_poc(start, end)

 *

 *		Clean and invalidate D-cache region to the Point of Coherency.

 *

 *	__inval_dcache_area(start, end)

 *	dcache_inval_poc(start, end)

 *

 *		Invalidate D-cache region to the Point of Coherency.

 *

 *	__clean_dcache_area_poc(start, end)

 *	dcache_clean_poc(start, end)

 *

 *		Clean D-cache region to the Point of Coherency.

 *

 *	__clean_dcache_area_pop(start, end)

 *	dcache_clean_pop(start, end)

 *

 *		Clean D-cache region to the Point of Persistence.

 *

 *	__clean_dcache_area_pou(start, end)

 *	dcache_clean_pou(start, end)

 *

 *		Clean D-cache region to the Point of Unification.

 */

extern void __flush_icache_range(unsigned long start, unsigned long end);

extern void invalidate_icache_range(unsigned long start, unsigned long end);

extern void __flush_dcache_area(unsigned long start, unsigned long end);

extern void __inval_dcache_area(unsigned long start, unsigned long end);

extern void __clean_dcache_area_poc(unsigned long start, unsigned long end);

extern void __clean_dcache_area_pop(unsigned long start, unsigned long end);

extern void __clean_dcache_area_pou(unsigned long start, unsigned long end);

extern long __flush_cache_user_range(unsigned long start, unsigned long end);

extern void caches_clean_inval_pou(unsigned long start, unsigned long end);

extern void icache_inval_pou(unsigned long start, unsigned long end);

extern void dcache_clean_inval_poc(unsigned long start, unsigned long end);

extern void dcache_inval_poc(unsigned long start, unsigned long end);

extern void dcache_clean_poc(unsigned long start, unsigned long end);

extern void dcache_clean_pop(unsigned long start, unsigned long end);

extern void dcache_clean_pou(unsigned long start, unsigned long end);

extern long caches_clean_inval_user_pou(unsigned long start, unsigned long end);

extern void sync_icache_aliases(unsigned long start, unsigned long end);



static inline void flush_icache_range(unsigned long start, unsigned long end)

{

	__flush_icache_range(start, end);

	caches_clean_inval_pou(start, end);



	/*

	 * IPI all online CPUs so that they undergo a context synchronization
@@ -135,7 +135,7 @@ extern void copy_to_user_page(struct vm_area_struct *, struct page *, 
#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1

extern void flush_dcache_page(struct page *);



static __always_inline void __flush_icache_all(void)

static __always_inline void icache_inval_all_pou(void)

{

	if (cpus_have_const_cap(ARM64_HAS_CACHE_DIC))

		return;

arch/arm64/include/asm/efi.h

+1 −1
Original line number Diff line number Diff line
@@ -137,7 +137,7 @@ void efi_virtmap_unload(void); 


static inline void efi_capsule_flush_cache_range(void *addr, int size)

{

	__flush_dcache_area((unsigned long)addr, (unsigned long)addr + size);

	dcache_clean_inval_poc((unsigned long)addr, (unsigned long)addr + size);

}



#endif /* _ASM_EFI_H */

arch/arm64/include/asm/kvm_mmu.h

+3 −3
Original line number Diff line number Diff line
@@ -181,7 +181,7 @@ static inline void *__kvm_vector_slot2addr(void *base, 
struct kvm;



#define kvm_flush_dcache_to_poc(a,l)	\

	__flush_dcache_area((unsigned long)(a), (unsigned long)(a)+(l))

	dcache_clean_inval_poc((unsigned long)(a), (unsigned long)(a)+(l))



static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu)

{
@@ -209,12 +209,12 @@ static inline void __invalidate_icache_guest_page(kvm_pfn_t pfn, 
{

	if (icache_is_aliasing()) {

		/* any kind of VIPT cache */

		__flush_icache_all();

		icache_inval_all_pou();

	} else if (is_kernel_in_hyp_mode() || !icache_is_vpipt()) {

		/* PIPT or VPIPT at EL2 (see comment in __kvm_tlb_flush_vmid_ipa) */

		void *va = page_address(pfn_to_page(pfn));



		invalidate_icache_range((unsigned long)va,

		icache_inval_pou((unsigned long)va,

					(unsigned long)va + size);

	}

}

arch/arm64/kernel/alternative.c

+1 −1
Original line number Diff line number Diff line
@@ -181,7 +181,7 @@ static void __nocfi __apply_alternatives(struct alt_region *region, bool is_modu 
	 */

	if (!is_module) {

		dsb(ish);

		__flush_icache_all();

		icache_inval_all_pou();

		isb();



		/* Ignore ARM64_CB bit from feature mask */