Commit fade7ad5 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nva3: split pm backend out from nv50 



This will end up quite different, it makes sense for it to be completely
separate.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent aee582de

drivers/gpu/drm/nouveau/Makefile

+2 −2
Original line number Diff line number Diff line
@@ -10,7 +10,7 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \ 
             nouveau_hw.o nouveau_calc.o nouveau_bios.o nouveau_i2c.o \

             nouveau_display.o nouveau_connector.o nouveau_fbcon.o \

             nouveau_dp.o nouveau_ramht.o \

	     nouveau_pm.o nouveau_volt.o nouveau_perf.o \

	     nouveau_pm.o nouveau_volt.o nouveau_perf.o nouveau_temp.o \

             nv04_timer.o \

             nv04_mc.o nv40_mc.o nv50_mc.o \

             nv04_fb.o nv10_fb.o nv30_fb.o nv40_fb.o nv50_fb.o nvc0_fb.o \
@@ -25,7 +25,7 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \ 
             nv04_crtc.o nv04_display.o nv04_cursor.o nv04_fbcon.o \

             nv10_gpio.o nv50_gpio.o \

	     nv50_calc.o \

	     nv04_pm.o nv50_pm.o nouveau_temp.o

	     nv04_pm.o nv50_pm.o nva3_pm.o



nouveau-$(CONFIG_DRM_NOUVEAU_DEBUG) += nouveau_debugfs.o

nouveau-$(CONFIG_COMPAT) += nouveau_ioc32.o

drivers/gpu/drm/nouveau/nouveau_pm.h

+6 −0
Original line number Diff line number Diff line
@@ -58,6 +58,12 @@ void *nv50_pm_clock_pre(struct drm_device *, struct nouveau_pm_level *, 
			u32 id, int khz);

void nv50_pm_clock_set(struct drm_device *, void *);



/* nva3_pm.c */

int nva3_pm_clock_get(struct drm_device *, u32 id);

void *nva3_pm_clock_pre(struct drm_device *, struct nouveau_pm_level *,

			u32 id, int khz);

void nva3_pm_clock_set(struct drm_device *, void *);



/* nouveau_temp.c */

void nouveau_temp_init(struct drm_device *dev);

void nouveau_temp_fini(struct drm_device *dev);

drivers/gpu/drm/nouveau/nouveau_state.c

+15 −3
Original line number Diff line number Diff line
@@ -375,9 +375,21 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) 
		engine->gpio.get		= nv50_gpio_get;

		engine->gpio.set		= nv50_gpio_set;

		engine->gpio.irq_enable		= nv50_gpio_irq_enable;

		switch (dev_priv->chipset) {

		case 0xa3:

		case 0xa5:

		case 0xa8:

		case 0xaf:

			engine->pm.clock_get	= nva3_pm_clock_get;

			engine->pm.clock_pre	= nva3_pm_clock_pre;

			engine->pm.clock_set	= nva3_pm_clock_set;

			break;

		default:

			engine->pm.clock_get	= nv50_pm_clock_get;

			engine->pm.clock_pre	= nv50_pm_clock_pre;

			engine->pm.clock_set	= nv50_pm_clock_set;

			break;

		}

		engine->pm.voltage_get		= nouveau_voltage_gpio_get;

		engine->pm.voltage_set		= nouveau_voltage_gpio_set;

		if (dev_priv->chipset >= 0x84)

drivers/gpu/drm/nouveau/nv50_pm.c

+19 −37
Original line number Diff line number Diff line
@@ -27,12 +27,6 @@ 
#include "nouveau_bios.h"

#include "nouveau_pm.h"



/*XXX: boards using limits 0x40 need fixing, the register layout

 *     is correct here, but, there's some other funny magic

 *     that modifies things, so it's not likely we'll set/read

 *     the correct timings yet..  working on it...

 */



struct nv50_pm_state {

	struct nouveau_pm_level *perflvl;

	struct pll_lims pll;
@@ -51,7 +45,6 @@ nv50_pm_clock_get(struct drm_device *dev, u32 id) 
	if (ret)

		return ret;



	if (pll.vco2.maxfreq) {

	reg0 = nv_rd32(dev, pll.reg + 0);

	reg1 = nv_rd32(dev, pll.reg + 4);

	P = (reg0 & 0x00070000) >> 16;
@@ -61,13 +54,6 @@ nv50_pm_clock_get(struct drm_device *dev, u32 id) 
	return ((pll.refclk * N / M) >> P);

}



	reg0 = nv_rd32(dev, pll.reg + 4);

	P = (reg0 & 0x003f0000) >> 16;

	N = (reg0 & 0x0000ff00) >> 8;

	M = (reg0 & 0x000000ff);

	return pll.refclk * N / M / P;

}



void *

nv50_pm_clock_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl,

		  u32 id, int khz)
@@ -125,7 +111,6 @@ nv50_pm_clock_set(struct drm_device *dev, void *pre_state) 
		nouveau_bios_run_init_table(dev, perflvl->memscript, NULL);

	}



	if (state->pll.vco2.maxfreq) {

	if (state->type == PLL_MEMORY) {

		nv_wr32(dev, 0x100210, 0);

		nv_wr32(dev, 0x1002dc, 1);
@@ -140,9 +125,6 @@ nv50_pm_clock_set(struct drm_device *dev, void *pre_state) 
		nv_wr32(dev, 0x1002dc, 0);

		nv_wr32(dev, 0x100210, 0x80000000);

	}

	} else {

		nv_wr32(dev, reg + 4, (P << 16) | (N << 8) | M);

	}



	kfree(state);

}

drivers/gpu/drm/nouveau/nva3_pm.c

0 → 100644
+95 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2010 Red Hat Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: Ben Skeggs

 */



#include "drmP.h"

#include "nouveau_drv.h"

#include "nouveau_bios.h"

#include "nouveau_pm.h"



/*XXX: boards using limits 0x40 need fixing, the register layout

 *     is correct here, but, there's some other funny magic

 *     that modifies things, so it's not likely we'll set/read

 *     the correct timings yet..  working on it...

 */



struct nva3_pm_state {

	struct pll_lims pll;

	int N, M, P;

};



int

nva3_pm_clock_get(struct drm_device *dev, u32 id)

{

	struct pll_lims pll;

	int P, N, M, ret;

	u32 reg;



	ret = get_pll_limits(dev, id, &pll);

	if (ret)

		return ret;



	reg = nv_rd32(dev, pll.reg + 4);

	P = (reg & 0x003f0000) >> 16;

	N = (reg & 0x0000ff00) >> 8;

	M = (reg & 0x000000ff);

	return pll.refclk * N / M / P;

}



void *

nva3_pm_clock_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl,

		  u32 id, int khz)

{

	struct nva3_pm_state *state;

	int dummy, ret;



	state = kzalloc(sizeof(*state), GFP_KERNEL);

	if (!state)

		return ERR_PTR(-ENOMEM);



	ret = get_pll_limits(dev, id, &state->pll);

	if (ret < 0) {

		kfree(state);

		return (ret == -ENOENT) ? NULL : ERR_PTR(ret);

	}



	ret = nv50_calc_pll2(dev, &state->pll, khz, &state->N, &dummy,

			     &state->M, &state->P);

	if (ret < 0) {

		kfree(state);

		return ERR_PTR(ret);

	}



	return state;

}



void

nva3_pm_clock_set(struct drm_device *dev, void *pre_state)

{

	struct nva3_pm_state *state = pre_state;

	u32 reg = state->pll.reg;



	nv_wr32(dev, reg + 4, (state->P << 16) | (state->N << 8) | state->M);

	kfree(state);

}