Commit fac73543 authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915: Don't read query SSEU for non-existent slice 0 on old platforms 



Pre-HSW platforms don't use the gt SSEU structures; this means that
calling intel_sseu_get_subslices() on slice 0 for these platforms will
trip a GEM_BUG_ON(slice >= sseu->max_slices) warning.

Let's move the DSS lookup for a DG2 workaround into a helper function
that will only get called after we've already decided that we're on a
DG2 platform.

Fixes: 645cc0b9 ("drm/i915/dg2: Add initial gt/ctx/engine workarounds")
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211112160107.1593906-1-matthew.d.roper@intel.com
parent 5f1176b4

drivers/gpu/drm/i915/gt/intel_workarounds.c

+9 −2
Original line number Diff line number Diff line
@@ -2019,11 +2019,18 @@ engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 
				    CMD_CCTL_MOCS_OVERRIDE(mocs, mocs));

	}

}



static bool needs_wa_1308578152(struct intel_engine_cs *engine)

{

	u64 dss_mask = intel_sseu_get_subslices(&engine->gt->info.sseu, 0);



	return (dss_mask & GENMASK(GEN_DSS_PER_GSLICE - 1, 0)) == 0;

}



static void

rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)

{

	struct drm_i915_private *i915 = engine->i915;

	u64 dss_mask = intel_sseu_get_subslices(&engine->gt->info.sseu, 0);



	if (IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) {

		/* Wa_14013392000:dg2_g11 */
@@ -2057,7 +2064,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 


	/* Wa_1308578152:dg2_g10 when first gslice is fused off */

	if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_C0) &&

	    (dss_mask & GENMASK(GEN_DSS_PER_GSLICE - 1, 0)) == 0) {

	    needs_wa_1308578152(engine)) {

		wa_masked_dis(wal, GEN12_CS_DEBUG_MODE1_CCCSUNIT_BE_COMMON,

			      GEN12_REPLAY_MODE_GRANULARITY);

	}