Commit fabcdf9b authored by Peter Zijlstra's avatar Peter Zijlstra Committed by Yunying Sun
Browse files

x86/cpu: Update Hybrids

mainline inclusion
from mainline-v6.6-rc1
commit 53544562
category: feature
feature: SRF core PMU support
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I8RWG5
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=535445621a66faa7050c21d9d668595116285648



Intel-SIG: commit 53544562 x86/cpu: Update Hybrids
Backport as a dependency for Sierra Forrest core PMU support.

-------------------------------------

Give the hybrid thingies their own section, appropriately between Core
and Atom.

Add the Raptor Lake uarch names.

Put Lunar Lake after Arrow Lake per interweb guidance.

Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
Acked-by: default avatarHans de Goede <hdegoede@redhat.com>
Link: https://lore.kernel.org/r/20230807150405.828551866@infradead.org


Signed-off-by: default avatarYunying Sun <yunying.sun@intel.com>
parent 08f0cd22
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+5 −3
Original line number Diff line number Diff line
@@ -95,8 +95,6 @@
#define INTEL_FAM6_ICELAKE_L		0x7E	/* Sunny Cove */
#define INTEL_FAM6_ICELAKE_NNPI		0x9D	/* Sunny Cove */

#define INTEL_FAM6_LAKEFIELD		0x8A	/* Sunny Cove / Tremont */

#define INTEL_FAM6_ROCKETLAKE		0xA7	/* Cypress Cove */

#define INTEL_FAM6_TIGERLAKE_L		0x8C	/* Willow Cove */
@@ -109,10 +107,14 @@
#define INTEL_FAM6_GRANITERAPIDS_X	0xAD
#define INTEL_FAM6_GRANITERAPIDS_D	0xAE

/* "Hybrid" Processors (P-Core/E-Core) */

#define INTEL_FAM6_LAKEFIELD		0x8A	/* Sunny Cove / Tremont */

#define INTEL_FAM6_ALDERLAKE		0x97	/* Golden Cove / Gracemont */
#define INTEL_FAM6_ALDERLAKE_L		0x9A	/* Golden Cove / Gracemont */

#define INTEL_FAM6_RAPTORLAKE		0xB7
#define INTEL_FAM6_RAPTORLAKE		0xB7	/* Raptor Cove / Enhanced Gracemont */
#define INTEL_FAM6_RAPTORLAKE_P		0xBA

#define INTEL_FAM6_METEORLAKE		0xAC