Commit fa50d6b8 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge tag 'coresight-next-v6.5' of... 

Merge tag 'coresight-next-v6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux

 into char-misc-next

Suzuki writes:

coresight: Updates for v6.5

CoreSight and hwtracing subsystem updates for v6.5 includes:

 - Fixes to the CTI module reference leaks. This involves,
   redesign of how the helper devices are tracked and CTI
   devices have been converted to helper devices.
 - Fix removal of the trctraceidr file from sysfs for ETMs.
 - Match all ETMv4 instances based on the ETMv4 architected
   registers and the CoreSight Component ID (CID), than having
   to add individual PIDs for CPUs.
 - Add support for Dummy CoreSight source and sink drivers.
 - Add James Clark as Reviewer for the CoreSight kernel drivers
 - Fixes to HiSilicon PCIe Tune and Trace Device driver

Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>

* tag 'coresight-next-v6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux: (27 commits)
  hwtracing: hisi_ptt: Fix potential sleep in atomic context
  hwtracing: hisi_ptt: Advertise PERF_PMU_CAP_NO_EXCLUDE for PTT PMU
  hwtracing: hisi_ptt: Export available filters through sysfs
  hwtracing: hisi_ptt: Add support for dynamically updating the filter list
  hwtracing: hisi_ptt: Factor out filter allocation and release operation
  coresight: dummy: Update type of mode parameter in dummy_{sink,source}_enable()
  Documentation: trace: Add documentation for Coresight Dummy Trace
  dt-bindings: arm: Add support for Coresight dummy trace
  Coresight: Add coresight dummy driver
  MAINTAINERS: coresight: Add James Clark as Reviewer
  coresight: etm4x: Match all ETM4 instances based on DEVARCH and DEVTYPE
  coresight: etm4x: Make etm4_remove_dev() return void
  coresight: etm4x: Fix missing trctraceidr file in sysfs
  coresight: Fix CTI module refcount leak by making it a helper device
  coresight: Enable and disable helper devices adjacent to the path
  coresight: Refactor out buffer allocation function for ETR
  coresight: Make refcount a property of the connection
  coresight: Store in-connections as well as out-connections
  coresight: Simplify connection fixup mechanism
  coresight: Store pointers to connections rather than an array of them
  ...
parents 92852219 6c50384e

Documentation/ABI/testing/sysfs-devices-hisi_ptt

+52 −0
Original line number Diff line number Diff line
@@ -59,3 +59,55 @@ Description: (RW) Control the allocated buffer watermark of outbound packets. 
		The available tune data is [0, 1, 2]. Writing a negative value

		will return an error, and out of range values will be converted

		to 2. The value indicates a probable level of the event.



What:		/sys/devices/hisi_ptt<sicl_id>_<core_id>/root_port_filters

Date:		May 2023

KernelVersion:	6.5

Contact:	Yicong Yang <yangyicong@hisilicon.com>

Description:	This directory contains the files providing the PCIe Root Port filters

		information used for PTT trace. Each file is named after the supported

		Root Port device name <domain>:<bus>:<device>.<function>.



		See the description of the "filter" in Documentation/trace/hisi-ptt.rst

		for more information.



What:		/sys/devices/hisi_ptt<sicl_id>_<core_id>/root_port_filters/multiselect

Date:		May 2023

KernelVersion:	6.5

Contact:	Yicong Yang <yangyicong@hisilicon.com>

Description:	(Read) Indicates if this kind of filter can be selected at the same

		time as others filters, or must be used on it's own. 1 indicates

		the former case and 0 indicates the latter.



What:		/sys/devices/hisi_ptt<sicl_id>_<core_id>/root_port_filters/<bdf>

Date:		May 2023

KernelVersion:	6.5

Contact:	Yicong Yang <yangyicong@hisilicon.com>

Description:	(Read) Indicates the filter value of this Root Port filter, which

		can be used to control the TLP headers to trace by the PTT trace.



What:		/sys/devices/hisi_ptt<sicl_id>_<core_id>/requester_filters

Date:		May 2023

KernelVersion:	6.5

Contact:	Yicong Yang <yangyicong@hisilicon.com>

Description:	This directory contains the files providing the PCIe Requester filters

		information used for PTT trace. Each file is named after the supported

		Endpoint device name <domain>:<bus>:<device>.<function>.



		See the description of the "filter" in Documentation/trace/hisi-ptt.rst

		for more information.



What:		/sys/devices/hisi_ptt<sicl_id>_<core_id>/requester_filters/multiselect

Date:		May 2023

KernelVersion:	6.5

Contact:	Yicong Yang <yangyicong@hisilicon.com>

Description:	(Read) Indicates if this kind of filter can be selected at the same

		time as others filters, or must be used on it's own. 1 indicates

		the former case and 0 indicates the latter.



What:		/sys/devices/hisi_ptt<sicl_id>_<core_id>/requester_filters/<bdf>

Date:		May 2023

KernelVersion:	6.5

Contact:	Yicong Yang <yangyicong@hisilicon.com>

Description:	(Read) Indicates the filter value of this Requester filter, which

		can be used to control the TLP headers to trace by the PTT trace.

Documentation/devicetree/bindings/arm/arm,coresight-dummy-sink.yaml

0 → 100644
+73 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/arm/arm,coresight-dummy-sink.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: ARM Coresight Dummy sink component



description: |

  CoreSight components are compliant with the ARM CoreSight architecture

  specification and can be connected in various topologies to suit a particular

  SoCs tracing needs. These trace components can generally be classified as

  sinks, links and sources. Trace data produced by one or more sources flows

  through the intermediate links connecting the source to the currently selected

  sink.



  The Coresight dummy sink component is for the specific coresight sink devices

  kernel don't have permission to access or configure, e.g., CoreSight EUD on

  Qualcomm platforms. It is a mini-USB hub implemented to support the USB-based

  debug and trace capabilities. For this device, a dummy driver is needed to

  register it as Coresight sink device in kernel side, so that path can be

  created in the driver. Then the trace flow would be transferred to EUD via

  coresight link of AP processor. It provides Coresight API for operations on

  dummy source devices, such as enabling and disabling them. It also provides

  the Coresight dummy source paths for debugging.



  The primary use case of the coresight dummy sink is to build path in kernel

  side for dummy sink component.



maintainers:

  - Mike Leach <mike.leach@linaro.org>

  - Suzuki K Poulose <suzuki.poulose@arm.com>

  - James Clark <james.clark@arm.com>

  - Mao Jinlong <quic_jinlmao@quicinc.com>

  - Hao Zhang <quic_hazha@quicinc.com>



properties:

  compatible:

    enum:

      - arm,coresight-dummy-sink



  in-ports:

    $ref: /schemas/graph.yaml#/properties/ports



    properties:

      port:

        description: Input connection from the Coresight Trace bus to

          dummy sink, such as Embedded USB debugger(EUD).



        $ref: /schemas/graph.yaml#/properties/port



required:

  - compatible

  - in-ports



additionalProperties: false



examples:

  # Minimum dummy sink definition. Dummy sink connect to coresight replicator.

  - |

    sink {

      compatible = "arm,coresight-dummy-sink";



      in-ports {

        port {

          eud_in_replicator_swao: endpoint {

            remote-endpoint = <&replicator_swao_out_eud>;

          };

        };

      };

    };



...

Documentation/devicetree/bindings/arm/arm,coresight-dummy-source.yaml

0 → 100644
+71 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/arm/arm,coresight-dummy-source.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: ARM Coresight Dummy source component



description: |

  CoreSight components are compliant with the ARM CoreSight architecture

  specification and can be connected in various topologies to suit a particular

  SoCs tracing needs. These trace components can generally be classified as

  sinks, links and sources. Trace data produced by one or more sources flows

  through the intermediate links connecting the source to the currently selected

  sink.



  The Coresight dummy source component is for the specific coresight source

  devices kernel don't have permission to access or configure. For some SOCs,

  there would be Coresight source trace components on sub-processor which

  are conneted to AP processor via debug bus. For these devices, a dummy driver

  is needed to register them as Coresight source devices, so that paths can be

  created in the driver. It provides Coresight API for operations on dummy

  source devices, such as enabling and disabling them. It also provides the

  Coresight dummy source paths for debugging.



  The primary use case of the coresight dummy source is to build path in kernel

  side for dummy source component.



maintainers:

  - Mike Leach <mike.leach@linaro.org>

  - Suzuki K Poulose <suzuki.poulose@arm.com>

  - James Clark <james.clark@arm.com>

  - Mao Jinlong <quic_jinlmao@quicinc.com>

  - Hao Zhang <quic_hazha@quicinc.com>



properties:

  compatible:

    enum:

      - arm,coresight-dummy-source



  out-ports:

    $ref: /schemas/graph.yaml#/properties/ports



    properties:

      port:

        description: Output connection from the source to Coresight

          Trace bus.

        $ref: /schemas/graph.yaml#/properties/port



required:

  - compatible

  - out-ports



additionalProperties: false



examples:

  # Minimum dummy source definition. Dummy source connect to coresight funnel.

  - |

    source {

      compatible = "arm,coresight-dummy-source";



      out-ports {

        port {

          dummy_riscv_out_funnel_swao: endpoint {

            remote-endpoint = <&funnel_swao_in_dummy_riscv>;

          };

        };

      };

    };



...

Documentation/driver-api/driver-model/devres.rst

+1 −0
Original line number Diff line number Diff line
@@ -364,6 +364,7 @@ MEM 
  devm_kmalloc_array()

  devm_kmemdup()

  devm_krealloc()

  devm_krealloc_array()

  devm_kstrdup()

  devm_kstrdup_const()

  devm_kvasprintf()

Documentation/trace/coresight/coresight-dummy.rst

0 → 100644
+32 −0
Original line number Diff line number Diff line 
.. SPDX-License-Identifier: GPL-2.0



=============================

Coresight Dummy Trace Module

=============================



    :Author:   Hao Zhang <quic_hazha@quicinc.com>

    :Date:     June 2023



Introduction

------------



The Coresight dummy trace module is for the specific devices that kernel don't

have permission to access or configure, e.g., CoreSight TPDMs on Qualcomm

platforms. For these devices, a dummy driver is needed to register them as

Coresight devices. The module may also be used to define components that may

not have any programming interfaces, so that paths can be created in the driver.

It provides Coresight API for operations on dummy devices, such as enabling and

disabling them. It also provides the Coresight dummy sink/source paths for

debugging.



Config details

--------------



There are two types of nodes, dummy sink and dummy source. These nodes

are available at ``/sys/bus/coresight/devices``.



Example output::



    $ ls -l /sys/bus/coresight/devices | grep dummy

    dummy_sink0 -> ../../../devices/platform/soc@0/soc@0:sink/dummy_sink0

    dummy_source0 -> ../../../devices/platform/soc@0/soc@0:source/dummy_source0