Commit fa3530be authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge branch 'mlxsw-add-port-range-matching-support' 

Petr Machata says:

====================
mlxsw: Add port range matching support

Ido Schimmel writes:

Add port range matching support in mlxsw as part of tc-flower offload.

Patches #1-#7 gradually add port range matching support in mlxsw. See
patch #3 to understand how port range matching is implemented in the
device.

Patches #8-#10 add selftests.
====================

Link: https://lore.kernel.org/r/cover.1689092769.git.petrm@nvidia.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents 9f4a7c93 209218e4

drivers/net/ethernet/mellanox/mlxsw/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -29,7 +29,7 @@ mlxsw_spectrum-objs := spectrum.o spectrum_buffers.o \ 
				   spectrum_nve.o spectrum_nve_vxlan.o \

				   spectrum_dpipe.o spectrum_trap.o \

				   spectrum_ethtool.o spectrum_policer.o \

				   spectrum_pgt.o

				   spectrum_pgt.o spectrum_port_range.o

mlxsw_spectrum-$(CONFIG_MLXSW_SPECTRUM_DCB)	+= spectrum_dcb.o

mlxsw_spectrum-$(CONFIG_PTP_1588_CLOCK)		+= spectrum_ptp.o

obj-$(CONFIG_MLXSW_MINIMAL)	+= mlxsw_minimal.o

drivers/net/ethernet/mellanox/mlxsw/core_acl_flex_keys.c

+1 −0
Original line number Diff line number Diff line
@@ -43,6 +43,7 @@ static const struct mlxsw_afk_element_info mlxsw_afk_element_infos[] = { 
	MLXSW_AFK_ELEMENT_INFO_BUF(DST_IP_32_63, 0x38, 4),

	MLXSW_AFK_ELEMENT_INFO_BUF(DST_IP_0_31, 0x3C, 4),

	MLXSW_AFK_ELEMENT_INFO_U32(FDB_MISS, 0x40, 0, 1),

	MLXSW_AFK_ELEMENT_INFO_U32(L4_PORT_RANGE, 0x40, 1, 16),

};



struct mlxsw_afk {

drivers/net/ethernet/mellanox/mlxsw/core_acl_flex_keys.h

+1 −0
Original line number Diff line number Diff line
@@ -36,6 +36,7 @@ enum mlxsw_afk_element { 
	MLXSW_AFK_ELEMENT_VIRT_ROUTER_MSB,

	MLXSW_AFK_ELEMENT_VIRT_ROUTER_LSB,

	MLXSW_AFK_ELEMENT_FDB_MISS,

	MLXSW_AFK_ELEMENT_L4_PORT_RANGE,

	MLXSW_AFK_ELEMENT_MAX,

};

drivers/net/ethernet/mellanox/mlxsw/reg.h

+73 −0
Original line number Diff line number Diff line
@@ -2799,6 +2799,78 @@ static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info) 
	mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info);

}



/* PPRR - Policy-Engine Port Range Register

 * ----------------------------------------

 * This register is used for configuring port range identification.

 */

#define MLXSW_REG_PPRR_ID 0x3008

#define MLXSW_REG_PPRR_LEN 0x14



MLXSW_REG_DEFINE(pprr, MLXSW_REG_PPRR_ID, MLXSW_REG_PPRR_LEN);



/* reg_pprr_ipv4

 * Apply port range register to IPv4 packets.

 * Access: RW

 */

MLXSW_ITEM32(reg, pprr, ipv4, 0x00, 31, 1);



/* reg_pprr_ipv6

 * Apply port range register to IPv6 packets.

 * Access: RW

 */

MLXSW_ITEM32(reg, pprr, ipv6, 0x00, 30, 1);



/* reg_pprr_src

 * Apply port range register to source L4 ports.

 * Access: RW

 */

MLXSW_ITEM32(reg, pprr, src, 0x00, 29, 1);



/* reg_pprr_dst

 * Apply port range register to destination L4 ports.

 * Access: RW

 */

MLXSW_ITEM32(reg, pprr, dst, 0x00, 28, 1);



/* reg_pprr_tcp

 * Apply port range register to TCP packets.

 * Access: RW

 */

MLXSW_ITEM32(reg, pprr, tcp, 0x00, 27, 1);



/* reg_pprr_udp

 * Apply port range register to UDP packets.

 * Access: RW

 */

MLXSW_ITEM32(reg, pprr, udp, 0x00, 26, 1);



/* reg_pprr_register_index

 * Index of Port Range Register being accessed.

 * Range is 0..cap_max_acl_l4_port_range-1.

 * Access: Index

 */

MLXSW_ITEM32(reg, pprr, register_index, 0x00, 0, 8);



/* reg_prrr_port_range_min

 * Minimum port range for comparison.

 * Match is defined as:

 * port_range_min <= packet_port <= port_range_max.

 * Access: RW

 */

MLXSW_ITEM32(reg, pprr, port_range_min, 0x04, 16, 16);



/* reg_prrr_port_range_max

 * Maximum port range for comparison.

 * Access: RW

 */

MLXSW_ITEM32(reg, pprr, port_range_max, 0x04, 0, 16);



static inline void mlxsw_reg_pprr_pack(char *payload, u8 register_index)

{

	MLXSW_REG_ZERO(pprr, payload);

	mlxsw_reg_pprr_register_index_set(payload, register_index);

}



/* PPBS - Policy-Engine Policy Based Switching Register

 * ----------------------------------------------------

 * This register retrieves and sets Policy Based Switching Table entries.
@@ -12819,6 +12891,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 
	MLXSW_REG(pacl),

	MLXSW_REG(pagt),

	MLXSW_REG(ptar),

	MLXSW_REG(pprr),

	MLXSW_REG(ppbs),

	MLXSW_REG(prcr),

	MLXSW_REG(pefa),

drivers/net/ethernet/mellanox/mlxsw/resources.h

+2 −0
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ enum mlxsw_res_id { 
	MLXSW_RES_ID_ACL_FLEX_KEYS,

	MLXSW_RES_ID_ACL_MAX_ACTION_PER_RULE,

	MLXSW_RES_ID_ACL_ACTIONS_PER_SET,

	MLXSW_RES_ID_ACL_MAX_L4_PORT_RANGE,

	MLXSW_RES_ID_ACL_MAX_ERPT_BANKS,

	MLXSW_RES_ID_ACL_MAX_ERPT_BANK_SIZE,

	MLXSW_RES_ID_ACL_MAX_LARGE_KEY_ID,
@@ -99,6 +100,7 @@ static u16 mlxsw_res_ids[] = { 
	[MLXSW_RES_ID_ACL_FLEX_KEYS] = 0x2910,

	[MLXSW_RES_ID_ACL_MAX_ACTION_PER_RULE] = 0x2911,

	[MLXSW_RES_ID_ACL_ACTIONS_PER_SET] = 0x2912,

	[MLXSW_RES_ID_ACL_MAX_L4_PORT_RANGE] = 0x2920,

	[MLXSW_RES_ID_ACL_MAX_ERPT_BANKS] = 0x2940,

	[MLXSW_RES_ID_ACL_MAX_ERPT_BANK_SIZE] = 0x2941,

	[MLXSW_RES_ID_ACL_MAX_LARGE_KEY_ID] = 0x2942,