Commit fa28030a authored by Vladimir Stempen's avatar Vladimir Stempen Committed by Alex Deucher
Browse files

drm/amd/display: increase hardware status wait time 



[Why]
Diagnostics reports exceptions generated when timeout waiting for
DISPCLK frequency divider change expires when testing ODM4to1.
Diagnostics reports exceptions generated when timeout waiting for OTG
busy status expires when disabling OTG during ODM4to1 test.

[How]
Increase HW status waiting time for DISPCLK frequency divider change and
OTG busy status when disable OTG.

Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: default avatarAriel Bernstein <Eric.Bernstein@amd.com>
Acked-by: default avatarQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: default avatarVladimir Stempen <vladimir.stempen@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e50f67cf

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

+2 −2
Original line number Diff line number Diff line
@@ -179,7 +179,7 @@ void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr, struct 
	} else if (dispclk_wdivider == 127 && current_dispclk_wdivider != 127) {

		REG_UPDATE(DENTIST_DISPCLK_CNTL,

				DENTIST_DISPCLK_WDIVIDER, 126);

		REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 100);

		REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000);

		for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

			struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;
@@ -206,7 +206,7 @@ void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr, struct 


	REG_UPDATE(DENTIST_DISPCLK_CNTL,

			DENTIST_DISPCLK_WDIVIDER, dispclk_wdivider);

	REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 1000);

	REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000);

	REG_UPDATE(DENTIST_DISPCLK_CNTL,

			DENTIST_DPPCLK_WDIVIDER, dppclk_wdivider);

	REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100);

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c

+1 −1
Original line number Diff line number Diff line
@@ -151,7 +151,7 @@ static bool optc32_disable_crtc(struct timing_generator *optc) 
	/* CRTC disabled, so disable  clock. */

	REG_WAIT(OTG_CLOCK_CONTROL,

			OTG_BUSY, 0,

			1, 100000);

			1, 150000);



	return true;

}