Commit fa0d9c06 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-fixes-2023-04-27' of... 

Merge tag 'drm-intel-next-fixes-2023-04-27' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-next

One cc stable for pipe source size check on SKL+

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ZEpbSG1ZOSVqzGLx@jlahtine-mobl.ger.corp.intel.com
parents 6f5a5e86 d944eafe

drivers/gpu/drm/i915/display/skl_scaler.c

+17 −0
Original line number Diff line number Diff line
@@ -111,6 +111,8 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, 
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	const struct drm_display_mode *adjusted_mode =

		&crtc_state->hw.adjusted_mode;

	int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);

	int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);

	int min_src_w, min_src_h, min_dst_w, min_dst_h;

	int max_src_w, max_src_h, max_dst_w, max_dst_h;
@@ -207,6 +209,21 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, 
		return -EINVAL;

	}



	/*

	 * The pipe scaler does not use all the bits of PIPESRC, at least

	 * on the earlier platforms. So even when we're scaling a plane

	 * the *pipe* source size must not be too large. For simplicity

	 * we assume the limits match the scaler source size limits. Might

	 * not be 100% accurate on all platforms, but good enough for now.

	 */

	if (pipe_src_w > max_src_w || pipe_src_h > max_src_h) {

		drm_dbg_kms(&dev_priv->drm,

			    "scaler_user index %u.%u: pipe src size %ux%u "

			    "is out of scaler range\n",

			    crtc->pipe, scaler_user, pipe_src_w, pipe_src_h);

		return -EINVAL;

	}



	/* mark this plane as a scaler user in crtc_state */

	scaler_state->scaler_users |= (1 << scaler_user);

	drm_dbg_kms(&dev_priv->drm, "scaler_user index %u.%u: "