Loading drivers/gpu/drm/nouveau/nouveau_bios.c +5 −5 Original line number Diff line number Diff line Loading @@ -4541,7 +4541,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, u16 type, int pclk, NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n", dcbent->type, dcbent->location, dcbent->or); for (i = 0; i < table[3]; i++) { otable = ROMPTR(bios, table[table[1] + (i * table[2])]); otable = ROMPTR(dev, table[table[1] + (i * table[2])]); if (otable && bios_encoder_match(dcbent, ROM32(otable[0]))) break; } Loading Loading @@ -5493,7 +5493,7 @@ bit_table(struct drm_device *dev, u8 id, struct bit_entry *bit) bit->version = entry[1]; bit->length = ROM16(entry[2]); bit->offset = ROM16(entry[4]); bit->data = ROMPTR(bios, entry[4]); bit->data = ROMPTR(dev, entry[4]); return 0; } Loading Loading @@ -5807,9 +5807,9 @@ parse_dcb_gpio_table(struct nvbios *bios) u8 *dcb, *gpio = NULL, *entry; int i; dcb = ROMPTR(bios, bios->data[0x36]); dcb = ROMPTR(dev, bios->data[0x36]); if (dcb[0] >= 0x30) { gpio = ROMPTR(bios, dcb[10]); gpio = ROMPTR(dev, dcb[10]); if (!gpio) goto no_table; Loading @@ -5818,7 +5818,7 @@ parse_dcb_gpio_table(struct nvbios *bios) recordlen = gpio[3]; } else if (dcb[0] >= 0x22 && dcb[-1] >= 0x13) { gpio = ROMPTR(bios, dcb[-15]); gpio = ROMPTR(dev, dcb[-15]); if (!gpio) goto no_table; Loading drivers/gpu/drm/nouveau/nouveau_bios.h +8 −3 Original line number Diff line number Diff line Loading @@ -34,9 +34,14 @@ #define DCB_LOC_ON_CHIP 0 #define ROM16(x) le16_to_cpu(*(uint16_t *)&(x)) #define ROM32(x) le32_to_cpu(*(uint32_t *)&(x)) #define ROMPTR(bios, x) (ROM16(x) ? &(bios)->data[ROM16(x)] : NULL) #define ROM16(x) le16_to_cpu(*(u16 *)&(x)) #define ROM32(x) le32_to_cpu(*(u32 *)&(x)) #define ROM48(x) ({ u8 *p = &(x); (u64)ROM16(p[4]) << 32 | ROM32(p[0]); }) #define ROM64(x) le64_to_cpu(*(u64 *)&(x)) #define ROMPTR(d,x) ({ \ struct drm_nouveau_private *dev_priv = (d)->dev_private; \ ROM16(x) ? &dev_priv->vbios.data[ROM16(x)] : NULL; \ }) struct bit_entry { uint8_t id; Loading drivers/gpu/drm/nouveau/nouveau_dp.c +3 −6 Original line number Diff line number Diff line Loading @@ -273,8 +273,6 @@ nouveau_dp_tu_update(struct drm_device *dev, int or, int link, u32 clk, u32 bpp) u8 * nouveau_dp_bios_data(struct drm_device *dev, struct dcb_entry *dcb, u8 **entry) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nvbios *bios = &dev_priv->vbios; struct bit_entry d; u8 *table; int i; Loading @@ -289,7 +287,7 @@ nouveau_dp_bios_data(struct drm_device *dev, struct dcb_entry *dcb, u8 **entry) return NULL; } table = ROMPTR(bios, d.data[0]); table = ROMPTR(dev, d.data[0]); if (!table) { NV_ERROR(dev, "displayport table pointer invalid\n"); return NULL; Loading @@ -306,7 +304,7 @@ nouveau_dp_bios_data(struct drm_device *dev, struct dcb_entry *dcb, u8 **entry) } for (i = 0; i < table[3]; i++) { *entry = ROMPTR(bios, table[table[1] + (i * table[2])]); *entry = ROMPTR(dev, table[table[1] + (i * table[2])]); if (*entry && bios_encoder_match(dcb, ROM32((*entry)[0]))) return table; } Loading Loading @@ -336,7 +334,6 @@ struct dp_state { static void dp_set_link_config(struct drm_device *dev, struct dp_state *dp) { struct drm_nouveau_private *dev_priv = dev->dev_private; int or = dp->or, link = dp->link; u8 *entry, sink[2]; u32 dp_ctrl; Loading @@ -360,7 +357,7 @@ dp_set_link_config(struct drm_device *dev, struct dp_state *dp) * table, that has (among other things) pointers to more scripts that * need to be executed, this time depending on link speed. */ entry = ROMPTR(&dev_priv->vbios, dp->entry[10]); entry = ROMPTR(dev, dp->entry[10]); if (entry) { if (dp->table[0] < 0x30) { while (dp->link_bw < (ROM16(entry[0]) * 10)) Loading drivers/gpu/drm/nouveau/nouveau_mem.c +2 −2 Original line number Diff line number Diff line Loading @@ -644,10 +644,10 @@ nouveau_mem_timing_init(struct drm_device *dev) return; if (P.version == 1) hdr = (struct nouveau_pm_tbl_header *) ROMPTR(bios, P.data[4]); hdr = (struct nouveau_pm_tbl_header *) ROMPTR(dev, P.data[4]); else if (P.version == 2) hdr = (struct nouveau_pm_tbl_header *) ROMPTR(bios, P.data[8]); hdr = (struct nouveau_pm_tbl_header *) ROMPTR(dev, P.data[8]); else { NV_WARN(dev, "unknown mem for BIT P %d\n", P.version); } Loading drivers/gpu/drm/nouveau/nouveau_perf.c +5 −6 Original line number Diff line number Diff line Loading @@ -41,7 +41,7 @@ legacy_perf_init(struct drm_device *dev) return; } perf = ROMPTR(bios, bmp[0x73]); perf = ROMPTR(dev, bmp[0x73]); if (!perf) { NV_DEBUG(dev, "No memclock table pointer found.\n"); return; Loading Loading @@ -87,7 +87,7 @@ nouveau_perf_timing(struct drm_device *dev, struct bit_entry *P, * ramcfg to select the correct subentry */ if (P->version == 2) { u8 *tmap = ROMPTR(bios, P->data[4]); u8 *tmap = ROMPTR(dev, P->data[4]); if (!tmap) { NV_DEBUG(dev, "no timing map pointer\n"); return NULL; Loading Loading @@ -140,7 +140,6 @@ nouveau_perf_voltage(struct drm_device *dev, struct bit_entry *P, struct nouveau_pm_level *perflvl) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nvbios *bios = &dev_priv->vbios; u8 *vmap; int id; Loading @@ -165,7 +164,7 @@ nouveau_perf_voltage(struct drm_device *dev, struct bit_entry *P, return; } vmap = ROMPTR(bios, P->data[32]); vmap = ROMPTR(dev, P->data[32]); if (!vmap) { NV_DEBUG(dev, "volt map table pointer invalid\n"); return; Loading Loading @@ -200,7 +199,7 @@ nouveau_perf_init(struct drm_device *dev) return; } perf = ROMPTR(bios, P.data[0]); perf = ROMPTR(dev, P.data[0]); version = perf[0]; headerlen = perf[1]; if (version < 0x40) { Loading @@ -218,7 +217,7 @@ nouveau_perf_init(struct drm_device *dev) return; } perf = ROMPTR(bios, bios->data[bios->offset + 0x94]); perf = ROMPTR(dev, bios->data[bios->offset + 0x94]); if (!perf) { NV_DEBUG(dev, "perf table pointer invalid\n"); return; Loading Loading
drivers/gpu/drm/nouveau/nouveau_bios.c +5 −5 Original line number Diff line number Diff line Loading @@ -4541,7 +4541,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, u16 type, int pclk, NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n", dcbent->type, dcbent->location, dcbent->or); for (i = 0; i < table[3]; i++) { otable = ROMPTR(bios, table[table[1] + (i * table[2])]); otable = ROMPTR(dev, table[table[1] + (i * table[2])]); if (otable && bios_encoder_match(dcbent, ROM32(otable[0]))) break; } Loading Loading @@ -5493,7 +5493,7 @@ bit_table(struct drm_device *dev, u8 id, struct bit_entry *bit) bit->version = entry[1]; bit->length = ROM16(entry[2]); bit->offset = ROM16(entry[4]); bit->data = ROMPTR(bios, entry[4]); bit->data = ROMPTR(dev, entry[4]); return 0; } Loading Loading @@ -5807,9 +5807,9 @@ parse_dcb_gpio_table(struct nvbios *bios) u8 *dcb, *gpio = NULL, *entry; int i; dcb = ROMPTR(bios, bios->data[0x36]); dcb = ROMPTR(dev, bios->data[0x36]); if (dcb[0] >= 0x30) { gpio = ROMPTR(bios, dcb[10]); gpio = ROMPTR(dev, dcb[10]); if (!gpio) goto no_table; Loading @@ -5818,7 +5818,7 @@ parse_dcb_gpio_table(struct nvbios *bios) recordlen = gpio[3]; } else if (dcb[0] >= 0x22 && dcb[-1] >= 0x13) { gpio = ROMPTR(bios, dcb[-15]); gpio = ROMPTR(dev, dcb[-15]); if (!gpio) goto no_table; Loading
drivers/gpu/drm/nouveau/nouveau_bios.h +8 −3 Original line number Diff line number Diff line Loading @@ -34,9 +34,14 @@ #define DCB_LOC_ON_CHIP 0 #define ROM16(x) le16_to_cpu(*(uint16_t *)&(x)) #define ROM32(x) le32_to_cpu(*(uint32_t *)&(x)) #define ROMPTR(bios, x) (ROM16(x) ? &(bios)->data[ROM16(x)] : NULL) #define ROM16(x) le16_to_cpu(*(u16 *)&(x)) #define ROM32(x) le32_to_cpu(*(u32 *)&(x)) #define ROM48(x) ({ u8 *p = &(x); (u64)ROM16(p[4]) << 32 | ROM32(p[0]); }) #define ROM64(x) le64_to_cpu(*(u64 *)&(x)) #define ROMPTR(d,x) ({ \ struct drm_nouveau_private *dev_priv = (d)->dev_private; \ ROM16(x) ? &dev_priv->vbios.data[ROM16(x)] : NULL; \ }) struct bit_entry { uint8_t id; Loading
drivers/gpu/drm/nouveau/nouveau_dp.c +3 −6 Original line number Diff line number Diff line Loading @@ -273,8 +273,6 @@ nouveau_dp_tu_update(struct drm_device *dev, int or, int link, u32 clk, u32 bpp) u8 * nouveau_dp_bios_data(struct drm_device *dev, struct dcb_entry *dcb, u8 **entry) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nvbios *bios = &dev_priv->vbios; struct bit_entry d; u8 *table; int i; Loading @@ -289,7 +287,7 @@ nouveau_dp_bios_data(struct drm_device *dev, struct dcb_entry *dcb, u8 **entry) return NULL; } table = ROMPTR(bios, d.data[0]); table = ROMPTR(dev, d.data[0]); if (!table) { NV_ERROR(dev, "displayport table pointer invalid\n"); return NULL; Loading @@ -306,7 +304,7 @@ nouveau_dp_bios_data(struct drm_device *dev, struct dcb_entry *dcb, u8 **entry) } for (i = 0; i < table[3]; i++) { *entry = ROMPTR(bios, table[table[1] + (i * table[2])]); *entry = ROMPTR(dev, table[table[1] + (i * table[2])]); if (*entry && bios_encoder_match(dcb, ROM32((*entry)[0]))) return table; } Loading Loading @@ -336,7 +334,6 @@ struct dp_state { static void dp_set_link_config(struct drm_device *dev, struct dp_state *dp) { struct drm_nouveau_private *dev_priv = dev->dev_private; int or = dp->or, link = dp->link; u8 *entry, sink[2]; u32 dp_ctrl; Loading @@ -360,7 +357,7 @@ dp_set_link_config(struct drm_device *dev, struct dp_state *dp) * table, that has (among other things) pointers to more scripts that * need to be executed, this time depending on link speed. */ entry = ROMPTR(&dev_priv->vbios, dp->entry[10]); entry = ROMPTR(dev, dp->entry[10]); if (entry) { if (dp->table[0] < 0x30) { while (dp->link_bw < (ROM16(entry[0]) * 10)) Loading
drivers/gpu/drm/nouveau/nouveau_mem.c +2 −2 Original line number Diff line number Diff line Loading @@ -644,10 +644,10 @@ nouveau_mem_timing_init(struct drm_device *dev) return; if (P.version == 1) hdr = (struct nouveau_pm_tbl_header *) ROMPTR(bios, P.data[4]); hdr = (struct nouveau_pm_tbl_header *) ROMPTR(dev, P.data[4]); else if (P.version == 2) hdr = (struct nouveau_pm_tbl_header *) ROMPTR(bios, P.data[8]); hdr = (struct nouveau_pm_tbl_header *) ROMPTR(dev, P.data[8]); else { NV_WARN(dev, "unknown mem for BIT P %d\n", P.version); } Loading
drivers/gpu/drm/nouveau/nouveau_perf.c +5 −6 Original line number Diff line number Diff line Loading @@ -41,7 +41,7 @@ legacy_perf_init(struct drm_device *dev) return; } perf = ROMPTR(bios, bmp[0x73]); perf = ROMPTR(dev, bmp[0x73]); if (!perf) { NV_DEBUG(dev, "No memclock table pointer found.\n"); return; Loading Loading @@ -87,7 +87,7 @@ nouveau_perf_timing(struct drm_device *dev, struct bit_entry *P, * ramcfg to select the correct subentry */ if (P->version == 2) { u8 *tmap = ROMPTR(bios, P->data[4]); u8 *tmap = ROMPTR(dev, P->data[4]); if (!tmap) { NV_DEBUG(dev, "no timing map pointer\n"); return NULL; Loading Loading @@ -140,7 +140,6 @@ nouveau_perf_voltage(struct drm_device *dev, struct bit_entry *P, struct nouveau_pm_level *perflvl) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nvbios *bios = &dev_priv->vbios; u8 *vmap; int id; Loading @@ -165,7 +164,7 @@ nouveau_perf_voltage(struct drm_device *dev, struct bit_entry *P, return; } vmap = ROMPTR(bios, P->data[32]); vmap = ROMPTR(dev, P->data[32]); if (!vmap) { NV_DEBUG(dev, "volt map table pointer invalid\n"); return; Loading Loading @@ -200,7 +199,7 @@ nouveau_perf_init(struct drm_device *dev) return; } perf = ROMPTR(bios, P.data[0]); perf = ROMPTR(dev, P.data[0]); version = perf[0]; headerlen = perf[1]; if (version < 0x40) { Loading @@ -218,7 +217,7 @@ nouveau_perf_init(struct drm_device *dev) return; } perf = ROMPTR(bios, bios->data[bios->offset + 0x94]); perf = ROMPTR(dev, bios->data[bios->offset + 0x94]); if (!perf) { NV_DEBUG(dev, "perf table pointer invalid\n"); return; Loading