Unverified Commit f9e394a2 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!7870 CVE-2024-35995 

Merge Pull Request from: @ci-robot 
 
PR sync from: liwei <liwei728@huawei.com>
https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/message/YMXQ3X6QOFR6TU2PRGILTLVE3QHTJQ6P/ 
CVE-2024-35995

Jarred White (2):
  ACPI: CPPC: Use access_width over bit_width for system memory accesses
  ACPI: CPPC: Fix bit_offset shift in MASK_VAL() macro

Rafael J. Wysocki (1):
  ACPI: CPPC: Fix up I/O port access in cpc_read()

Steven Noonan (1):
  ACPI: CPPC: Implement support for SystemIO registers

Vanshidhar Konda (1):
  ACPI: CPPC: Fix access width used for PCC registers


-- 
2.25.1
 
https://gitee.com/src-openeuler/kernel/issues/I9QRD6 
 
Link:https://gitee.com/openeuler/kernel/pulls/7870

 

Reviewed-by: default avatarXiongfeng Wang <wangxiongfeng2@huawei.com>
Signed-off-by: default avatarJialin Zhang <zhangjialin11@huawei.com>
parents 02edb9f3 867939ca

drivers/acpi/cppc_acpi.c

+132 −42
Original line number Diff line number Diff line
@@ -129,6 +129,8 @@ static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr); 
 */

#define NUM_RETRIES 500ULL



#define OVER_16BTS_MASK ~0xFFFFULL



#define define_one_cppc_ro(_name)		\

static struct kobj_attribute _name =		\

__ATTR(_name, 0444, show_##_name, NULL)
@@ -162,6 +164,13 @@ show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_freq); 
show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf);

show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time);



/* Check for valid access_width, otherwise, fallback to using bit_width */

#define GET_BIT_WIDTH(reg) ((reg)->access_width ? (8 << ((reg)->access_width - 1)) : (reg)->bit_width)



/* Shift and apply the mask for CPC reads/writes */

#define MASK_VAL(reg, val) (((val) >> (reg)->bit_offset) & 			\

					GENMASK(((reg)->bit_width) - 1, 0))



static ssize_t show_feedback_ctrs(struct kobject *kobj,

		struct kobj_attribute *attr, char *buf)

{
@@ -870,15 +879,34 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr) 
			} else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {

				if (gas_t->address) {

					void __iomem *addr;

					size_t access_width;



					addr = ioremap(gas_t->address, gas_t->bit_width/8);

					access_width = GET_BIT_WIDTH(gas_t) / 8;

					addr = ioremap(gas_t->address, access_width);

					if (!addr)

						goto out_free;

					cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr;

				}

			} else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {

				if (gas_t->access_width < 1 || gas_t->access_width > 3) {

					/*

					 * 1 = 8-bit, 2 = 16-bit, and 3 = 32-bit.

					 * SystemIO doesn't implement 64-bit

					 * registers.

					 */

					pr_debug("Invalid access width %d for SystemIO register\n",

						gas_t->access_width);

					goto out_free;

				}

				if (gas_t->address & OVER_16BTS_MASK) {

					/* SystemIO registers use 16-bit integer addresses */

					pr_debug("Invalid IO port %llu for SystemIO register\n",

						gas_t->address);

					goto out_free;

				}

			} else {

				if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) {

					/* Support only PCC ,SYS MEM and FFH type regs */

					/* Support only PCC, SystemMemory, SystemIO, and FFH type regs. */

					pr_debug("Unsupported register type: %d\n", gas_t->space_id);

					goto out_free;

				}
@@ -1044,6 +1072,7 @@ static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val) 
{

	int ret_val = 0;

	void __iomem *vaddr = 0;

	int size;

	int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);

	struct cpc_reg *reg = &reg_res->cpc_entry.reg;
@@ -1053,17 +1082,40 @@ static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val) 
	}



	*val = 0;

	if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0)

	size = GET_BIT_WIDTH(reg);



	if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {

		u32 val_u32;

		acpi_status status;



		status = acpi_os_read_port((acpi_io_address)reg->address,

					   &val_u32, size);

		if (ACPI_FAILURE(status)) {

			pr_debug("Error: Failed to read SystemIO port %llx\n",

				 reg->address);

			return -EFAULT;

		}



		*val = val_u32;

		return 0;

	} else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) {

		/*

		 * For registers in PCC space, the register size is determined

		 * by the bit width field; the access size is used to indicate

		 * the PCC subspace id.

		 */

		size = reg->bit_width;

		vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);

	}

	else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)

		vaddr = reg_res->sys_mem_vaddr;

	else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)

		return cpc_read_ffh(cpu, reg, val);

	else

		return acpi_os_read_memory((acpi_physical_address)reg->address,

				val, reg->bit_width);

				val, size);



	switch (reg->bit_width) {

	switch (size) {

	case 8:

		*val = readb_relaxed(vaddr);

		break;
@@ -1077,32 +1129,65 @@ static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val) 
		*val = readq_relaxed(vaddr);

		break;

	default:

		if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {

			pr_debug("Error: Cannot read %u bit width from system memory: 0x%llx\n",

				size, reg->address);

		} else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {

			pr_debug("Error: Cannot read %u bit width from PCC for ss: %d\n",

				 reg->bit_width, pcc_ss_id);

			ret_val = -EFAULT;

				size, pcc_ss_id);

		}

		return -EFAULT;

	}



	return ret_val;

	if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)

		*val = MASK_VAL(reg, *val);



	return 0;

}



static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)

{

	int ret_val = 0;

	void __iomem *vaddr = 0;

	int size;

	int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);

	struct cpc_reg *reg = &reg_res->cpc_entry.reg;



	if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0)

	size = GET_BIT_WIDTH(reg);



	if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {

		acpi_status status;



		status = acpi_os_write_port((acpi_io_address)reg->address,

					    (u32)val, size);

		if (ACPI_FAILURE(status)) {

			pr_debug("Error: Failed to write SystemIO port %llx\n",

				 reg->address);

			return -EFAULT;

		}



		return 0;

	} else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) {

		/*

		 * For registers in PCC space, the register size is determined

		 * by the bit width field; the access size is used to indicate

		 * the PCC subspace id.

		 */

		size = reg->bit_width;

		vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);

	}

	else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)

		vaddr = reg_res->sys_mem_vaddr;

	else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)

		return cpc_write_ffh(cpu, reg, val);

	else

		return acpi_os_write_memory((acpi_physical_address)reg->address,

				val, reg->bit_width);

				val, size);



	switch (reg->bit_width) {

	if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)

		val = MASK_VAL(reg, val);



	switch (size) {

	case 8:

		writeb_relaxed(val, vaddr);

		break;
@@ -1116,8 +1201,13 @@ static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val) 
		writeq_relaxed(val, vaddr);

		break;

	default:

		if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {

			pr_debug("Error: Cannot write %u bit width to system memory: 0x%llx\n",

				size, reg->address);

		} else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {

			pr_debug("Error: Cannot write %u bit width to PCC for ss: %d\n",

				 reg->bit_width, pcc_ss_id);

				size, pcc_ss_id);

		}

		ret_val = -EFAULT;

		break;

	}