Unverified Commit f9ace4ed authored by Vitaly Wool's avatar Vitaly Wool Committed by Palmer Dabbelt
Browse files

riscv: remove .text section size limitation for XIP 



Currently there's a limit of 8MB for the .text section of a RISC-V
image in the XIP case. This breaks compilation of many automatic
builds and is generally inconvenient. This patch removes that
limitation and optimizes XIP image file size at the same time.

Signed-off-by: default avatarVitaly Wool <vitaly.wool@konsulko.com>
Signed-off-by: default avatarPalmer Dabbelt <palmerdabbelt@google.com>
parent 241527bb

arch/riscv/include/asm/pgtable.h

+4 −2
Original line number Diff line number Diff line
@@ -75,7 +75,8 @@ 
#endif



#ifdef CONFIG_XIP_KERNEL

#define XIP_OFFSET		SZ_8M

#define XIP_OFFSET		SZ_32M

#define XIP_OFFSET_MASK		(SZ_32M - 1)

#else

#define XIP_OFFSET		0

#endif
@@ -97,7 +98,8 @@ 
#ifdef CONFIG_XIP_KERNEL

#define XIP_FIXUP(addr) ({							\

	uintptr_t __a = (uintptr_t)(addr);					\

	(__a >= CONFIG_XIP_PHYS_ADDR && __a < CONFIG_XIP_PHYS_ADDR + SZ_16M) ?	\

	(__a >= CONFIG_XIP_PHYS_ADDR && \

	 __a < CONFIG_XIP_PHYS_ADDR + XIP_OFFSET * 2) ?	\

		__a - CONFIG_XIP_PHYS_ADDR + CONFIG_PHYS_RAM_BASE - XIP_OFFSET :\

		__a;								\

	})

arch/riscv/kernel/head.S

+12 −0
Original line number Diff line number Diff line
@@ -20,10 +20,20 @@ 
	REG_L t0, _xip_fixup

	add \reg, \reg, t0

.endm

.macro XIP_FIXUP_FLASH_OFFSET reg

	la t1, __data_loc

	li t0, XIP_OFFSET_MASK

	and t1, t1, t0

	li t1, XIP_OFFSET

	sub t0, t0, t1

	sub \reg, \reg, t0

.endm

_xip_fixup: .dword CONFIG_PHYS_RAM_BASE - CONFIG_XIP_PHYS_ADDR - XIP_OFFSET

#else

.macro XIP_FIXUP_OFFSET reg

.endm

.macro XIP_FIXUP_FLASH_OFFSET reg

.endm

#endif /* CONFIG_XIP_KERNEL */



__HEAD
@@ -266,6 +276,7 @@ pmp_done: 
	la a3, hart_lottery

	mv a2, a3

	XIP_FIXUP_OFFSET a2

	XIP_FIXUP_FLASH_OFFSET a3

	lw t1, (a3)

	amoswap.w t0, t1, (a2)

	/* first time here if hart_lottery in RAM is not set */
@@ -304,6 +315,7 @@ clear_bss_done: 
	XIP_FIXUP_OFFSET sp

#ifdef CONFIG_BUILTIN_DTB

	la a0, __dtb_start

	XIP_FIXUP_OFFSET a0

#else

	mv a0, s1

#endif /* CONFIG_BUILTIN_DTB */

arch/riscv/kernel/vmlinux-xip.lds.S

+7 −3
Original line number Diff line number Diff line
@@ -64,8 +64,11 @@ SECTIONS 
/*

 * From this point, stuff is considered writable and will be copied to RAM

 */

	__data_loc = ALIGN(16);		/* location in file */

	. = LOAD_OFFSET + XIP_OFFSET;	/* location in memory */

	__data_loc = ALIGN(PAGE_SIZE);		/* location in file */

	. = KERNEL_LINK_ADDR + XIP_OFFSET;	/* location in memory */



#undef LOAD_OFFSET

#define LOAD_OFFSET (KERNEL_LINK_ADDR + XIP_OFFSET - (__data_loc & XIP_OFFSET_MASK))



	_sdata = .;			/* Start of data section */

	_data = .;
@@ -96,7 +99,6 @@ SECTIONS 
		KEEP(*(__soc_builtin_dtb_table))

		__soc_builtin_dtb_table_end = .;

	}

	PERCPU_SECTION(L1_CACHE_BYTES)



	. = ALIGN(8);

	.alternative : {
@@ -122,6 +124,8 @@ SECTIONS 


	BSS_SECTION(PAGE_SIZE, PAGE_SIZE, 0)



	PERCPU_SECTION(L1_CACHE_BYTES)



	.rel.dyn : AT(ADDR(.rel.dyn) - LOAD_OFFSET) {

		*(.rel.dyn*)

	}

arch/riscv/mm/init.c

+3 −4
Original line number Diff line number Diff line
@@ -41,7 +41,7 @@ phys_addr_t phys_ram_base __ro_after_init; 
EXPORT_SYMBOL(phys_ram_base);



#ifdef CONFIG_XIP_KERNEL

extern char _xiprom[], _exiprom[];

extern char _xiprom[], _exiprom[], __data_loc;

#endif



unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]
@@ -454,10 +454,9 @@ static uintptr_t __init best_map_size(phys_addr_t base, phys_addr_t size) 
/* called from head.S with MMU off */

asmlinkage void __init __copy_data(void)

{

	void *from = (void *)(&_sdata);

	void *end = (void *)(&_end);

	void *from = (void *)(&__data_loc);

	void *to = (void *)CONFIG_PHYS_RAM_BASE;

	size_t sz = (size_t)(end - from + 1);

	size_t sz = (size_t)((uintptr_t)(&_end) - (uintptr_t)(&_sdata));



	memcpy(to, from, sz);

}