Commit f9900dd0 authored by Zhengjun Xing's avatar Zhengjun Xing Committed by Arnaldo Carvalho de Melo
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perf vendor events intel: Add core event list for Alderlake 

Add JSON core events for Alderlake to perf.

It is a hybrid event list for both Atom and Core.

Based on JSON list v1.06:

https://download.01.org/perfmon/ADL/



Signed-off-by: default avatarZhengjun Xing <zhengjun.xing@linux.intel.com>
Acked-by: default avatarIan Rogers <irogers@google.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/r/20220224162329.1975081-1-zhengjun.xing@linux.intel.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 6b342707

tools/perf/pmu-events/arch/x86/alderlake/cache.json

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tools/perf/pmu-events/arch/x86/alderlake/floating-point.json

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[

    {

        "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5",

        "EventCode": "0xc3",

        "EventName": "MACHINE_CLEARS.FP_ASSIST",

        "PEBScounters": "0,1,2,3,4,5",

        "SampleAfterValue": "20003",

        "UMask": "0x4",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt).",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5",

        "EventCode": "0xc2",

        "EventName": "UOPS_RETIRED.FPDIV",

        "PEBS": "1",

        "PEBScounters": "0,1,2,3,4,5",

        "SampleAfterValue": "2000003",

        "UMask": "0x8",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "TBD",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "CounterMask": "1",

        "EventCode": "0xb0",

        "EventName": "ARITH.FPDIV_ACTIVE",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "1000003",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts all microcode FP assists.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc1",

        "EventName": "ASSISTS.FP",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "100003",

        "UMask": "0x2",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "TBD",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc1",

        "EventName": "ASSISTS.SSE_AVX_MIX",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "1000003",

        "UMask": "0x10",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "TBD",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xb3",

        "EventName": "FP_ARITH_DISPATCHED.PORT_0",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "2000003",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "TBD",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xb3",

        "EventName": "FP_ARITH_DISPATCHED.PORT_1",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "2000003",

        "UMask": "0x2",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "TBD",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xb3",

        "EventName": "FP_ARITH_DISPATCHED.PORT_5",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "2000003",

        "UMask": "0x4",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc7",

        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "100003",

        "UMask": "0x4",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc7",

        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "100003",

        "UMask": "0x8",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc7",

        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "100003",

        "UMask": "0x10",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc7",

        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "100003",

        "UMask": "0x20",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc7",

        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc7",

        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "100003",

        "UMask": "0x2",

        "Unit": "cpu_core"

    }

]
 
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tools/perf/pmu-events/arch/x86/alderlake/frontend.json

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tools/perf/pmu-events/arch/x86/alderlake/memory.json

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[

    {

        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires.",

        "Counter": "0,1,2,3,4,5",

        "EventCode": "0x05",

        "EventName": "LD_HEAD.ANY_AT_RET",

        "SampleAfterValue": "1000003",

        "UMask": "0xff",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring.",

        "Counter": "0,1,2,3",

        "EventCode": "0x05",

        "EventName": "LD_HEAD.L1_BOUND_AT_RET",

        "SampleAfterValue": "1000003",

        "UMask": "0xf4",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to other block cases when load subsequently retires when load subsequently retires.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5",

        "EventCode": "0x05",

        "EventName": "LD_HEAD.OTHER_AT_RET",

        "PEBScounters": "0,1,2,3,4,5",

        "SampleAfterValue": "1000003",

        "UMask": "0xc0",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a pagewalk when load subsequently retires.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5",

        "EventCode": "0x05",

        "EventName": "LD_HEAD.PGWALK_AT_RET",

        "PEBScounters": "0,1,2,3,4,5",

        "SampleAfterValue": "1000003",

        "UMask": "0xa0",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a store address match when load subsequently retires.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5",

        "EventCode": "0x05",

        "EventName": "LD_HEAD.ST_ADDR_AT_RET",

        "PEBScounters": "0,1,2,3,4,5",

        "SampleAfterValue": "1000003",

        "UMask": "0x84",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5",

        "EventCode": "0xc3",

        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",

        "PEBScounters": "0,1,2,3,4,5",

        "SampleAfterValue": "20003",

        "UMask": "0x2",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3F84400001",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_RFO.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3F84400002",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "CounterMask": "6",

        "EventCode": "0xa3",

        "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "1000003",

        "UMask": "0x6",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Number of machine clears due to memory ordering conflicts.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc3",

        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "100003",

        "UMask": "0x2",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "CounterMask": "2",

        "EventCode": "0x47",

        "EventName": "MEMORY_ACTIVITY.CYCLES_L1D_MISS",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "1000003",

        "UMask": "0x2",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "CounterMask": "3",

        "EventCode": "0x47",

        "EventName": "MEMORY_ACTIVITY.STALLS_L1D_MISS",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "1000003",

        "UMask": "0x3",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "TBD",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "CounterMask": "5",

        "EventCode": "0x47",

        "EventName": "MEMORY_ACTIVITY.STALLS_L2_MISS",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "1000003",

        "UMask": "0x5",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "TBD",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "CounterMask": "9",

        "EventCode": "0x47",

        "EventName": "MEMORY_ACTIVITY.STALLS_L3_MISS",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "1000003",

        "UMask": "0x9",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",

        "CollectPEBSRecord": "2",

        "Counter": "1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xcd",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x80",

        "PEBS": "2",

        "PEBScounters": "1,2,3,4,5,6,7",

        "SampleAfterValue": "1009",

        "TakenAlone": "1",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",

        "CollectPEBSRecord": "2",

        "Counter": "1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xcd",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x10",

        "PEBS": "2",

        "PEBScounters": "1,2,3,4,5,6,7",

        "SampleAfterValue": "20011",

        "TakenAlone": "1",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",

        "CollectPEBSRecord": "2",

        "Counter": "1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xcd",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x100",

        "PEBS": "2",

        "PEBScounters": "1,2,3,4,5,6,7",

        "SampleAfterValue": "503",

        "TakenAlone": "1",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",

        "CollectPEBSRecord": "2",

        "Counter": "1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xcd",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x20",

        "PEBS": "2",

        "PEBScounters": "1,2,3,4,5,6,7",

        "SampleAfterValue": "100007",

        "TakenAlone": "1",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",

        "CollectPEBSRecord": "2",

        "Counter": "1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xcd",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x4",

        "PEBS": "2",

        "PEBScounters": "1,2,3,4,5,6,7",

        "SampleAfterValue": "100003",

        "TakenAlone": "1",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",

        "CollectPEBSRecord": "2",

        "Counter": "1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xcd",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x200",

        "PEBS": "2",

        "PEBScounters": "1,2,3,4,5,6,7",

        "SampleAfterValue": "101",

        "TakenAlone": "1",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",

        "CollectPEBSRecord": "2",

        "Counter": "1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xcd",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x40",

        "PEBS": "2",

        "PEBScounters": "1,2,3,4,5,6,7",

        "SampleAfterValue": "2003",

        "TakenAlone": "1",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",

        "CollectPEBSRecord": "2",

        "Counter": "1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xcd",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x8",

        "PEBS": "2",

        "PEBScounters": "1,2,3,4,5,6,7",

        "SampleAfterValue": "50021",

        "TakenAlone": "1",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Retired instructions with at least 1 store uop. This PEBS event is the trigger for stores sampled by the PEBS Store Facility.",

        "CollectPEBSRecord": "2",

        "Data_LA": "1",

        "EventCode": "0xcd",

        "EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE",

        "PEBS": "2",

        "SampleAfterValue": "1000003",

        "UMask": "0x2",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0x2A,0x2B",

        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3FBFC00001",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0x2A,0x2B",

        "EventName": "OCR.DEMAND_RFO.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3FBFC00002",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "Unit": "cpu_core"

    }

]
 
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tools/perf/pmu-events/arch/x86/alderlake/other.json

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[

    {

        "BriefDescription": "Counts demand data reads that have any type of response.",

        "Counter": "0,1,2,3",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x10001",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",

        "Counter": "0,1,2,3",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x10002",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts streaming stores that have any type of response.",

        "Counter": "0,1,2,3",

        "EventCode": "0xB7",

        "EventName": "OCR.STREAMING_WR.ANY_RESPONSE",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x10800",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc1",

        "EventName": "ASSISTS.ANY",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "100003",

        "UMask": "0x1f",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Count all other microcode assist beyond FP, AVX_TILE_MIX and A/D assists (counted by their own sub-events). This includes assists at uop writeback like AVX* load/store (non-FP) assists, Null Assist in SNC (due to lack of FP precision format convert with FMA3x3 uarch) or assists generated by ROB (like assists to due to Missprediction for FSW register - fixed in SNC)",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc1",

        "EventName": "ASSISTS.HARDWARE",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "100003",

        "UMask": "0x4",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "TBD",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc1",

        "EventName": "ASSISTS.PAGE_FAULT",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "1000003",

        "UMask": "0x8",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "TBD",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "EventCode": "0x28",

        "EventName": "CORE_POWER.LICENSE_1",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "200003",

        "UMask": "0x2",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "TBD",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "EventCode": "0x28",

        "EventName": "CORE_POWER.LICENSE_2",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "200003",

        "UMask": "0x4",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "TBD",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "EventCode": "0x28",

        "EventName": "CORE_POWER.LICENSE_3",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "200003",

        "UMask": "0x8",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts demand data reads that have any type of response.",

        "Counter": "0,1,2,3",

        "EventCode": "0x2A,0x2B",

        "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x10001",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",

        "Counter": "0,1,2,3",

        "EventCode": "0x2A,0x2B",

        "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x10002",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts streaming stores that have any type of response.",

        "Counter": "0,1,2,3",

        "EventCode": "0x2A,0x2B",

        "EventName": "OCR.STREAMING_WR.ANY_RESPONSE",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x10800",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "TBD",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "CounterMask": "1",

        "EventCode": "0x2d",

        "EventName": "XQ.FULL_CYCLES",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "1000003",

        "UMask": "0x1",

        "Unit": "cpu_core"

    }

]
 
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