Commit f98c2dfe authored Sep 23, 2022 by Peng Fan Committed by Shawn Guo Oct 24, 2022

arm64: dts: imx8m: align anatop with bindings



The CCM ANALOG module is used for generate PLLs, align the node
with DT bindings

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

parent 8fb7256a

arch/arm64/boot/dts/freescale/imx8mm.dtsi

+3 −2

Original line number	Diff line number	Diff line
		@@ -573,9 +573,10 @@
		};
		};

		anatop: anatop@30360000 {
		compatible = "fsl,imx8mm-anatop", "syscon";
		anatop: clock-controller@30360000 {
		compatible = "fsl,imx8mm-anatop";
		reg = <0x30360000 0x10000>;
		#clock-cells = <1>;
		};

		snvs: snvs@30370000 {

arch/arm64/boot/dts/freescale/imx8mn.dtsi

+3 −3

Original line number	Diff line number	Diff line
		@@ -576,10 +576,10 @@
		};
		};

		anatop: anatop@30360000 {
		compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop",
		"syscon";
		anatop: clock-controller@30360000 {
		compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop";
		reg = <0x30360000 0x10000>;
		#clock-cells = <1>;
		};

		snvs: snvs@30370000 {

arch/arm64/boot/dts/freescale/imx8mp.dtsi

+3 −3

Original line number	Diff line number	Diff line
		@@ -441,10 +441,10 @@
		};
		};

		anatop: anatop@30360000 {
		compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop",
		"syscon";
		anatop: clock-controller@30360000 {
		compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop";
		reg = <0x30360000 0x10000>;
		#clock-cells = <1>;
		};

		snvs: snvs@30370000 {

arch/arm64/boot/dts/freescale/imx8mq.dtsi

+3 −2

Original line number	Diff line number	Diff line
		@@ -605,10 +605,11 @@
		};
		};

		anatop: syscon@30360000 {
		compatible = "fsl,imx8mq-anatop", "syscon";
		anatop: clock-controller@30360000 {
		compatible = "fsl,imx8mq-anatop";
		reg = <0x30360000 0x10000>;
		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
		#clock-cells = <1>;
		};

		snvs: snvs@30370000 {