Commit f96d67a8 authored by Will Deacon's avatar Will Deacon
Browse files

Merge branch 'for-next/boot' into for-next/core 

* for-next/boot: (34 commits)
  arm64: fix KASAN_INLINE
  arm64: Add an override for ID_AA64SMFR0_EL1.FA64
  arm64: Add the arm64.nosve command line option
  arm64: Add the arm64.nosme command line option
  arm64: Expose a __check_override primitive for oddball features
  arm64: Allow the idreg override to deal with variable field width
  arm64: Factor out checking of a feature against the override into a macro
  arm64: Allow sticky E2H when entering EL1
  arm64: Save state of HCR_EL2.E2H before switch to EL1
  arm64: Rename the VHE switch to "finalise_el2"
  arm64: mm: fix booting with 52-bit address space
  arm64: head: remove __PHYS_OFFSET
  arm64: lds: use PROVIDE instead of conditional definitions
  arm64: setup: drop early FDT pointer helpers
  arm64: head: avoid relocating the kernel twice for KASLR
  arm64: kaslr: defer initialization to initcall where permitted
  arm64: head: record CPU boot mode after enabling the MMU
  arm64: head: populate kernel page tables with MMU and caches on
  arm64: head: factor out TTBR1 assignment into a macro
  arm64: idreg-override: use early FDT mapping in ID map
  ...
parents 92867739 1191b625

Documentation/admin-guide/kernel-parameters.txt

+6 −0
Original line number Diff line number Diff line
@@ -400,6 +400,12 @@ 
	arm64.nomte	[ARM64] Unconditionally disable Memory Tagging Extension

			support



	arm64.nosve	[ARM64] Unconditionally disable Scalable Vector

			Extension support



	arm64.nosme	[ARM64] Unconditionally disable Scalable Matrix

			Extension support



	ataflop=	[HW,M68k]



	atarimouse=	[HW,MOUSE] Atari Mouse

Documentation/virt/kvm/arm/hyp-abi.rst

+6 −5
Original line number Diff line number Diff line
@@ -60,12 +60,13 @@ these functions (see arch/arm{,64}/include/asm/virt.h): 


* ::



    x0 = HVC_VHE_RESTART (arm64 only)

    x0 = HVC_FINALISE_EL2 (arm64 only)



  Attempt to upgrade the kernel's exception level from EL1 to EL2 by enabling

  the VHE mode. This is conditioned by the CPU supporting VHE, the EL2 MMU

  being off, and VHE not being disabled by any other means (command line

  option, for example).

  Finish configuring EL2 depending on the command-line options,

  including an attempt to upgrade the kernel's exception level from

  EL1 to EL2 by enabling the VHE mode. This is conditioned by the CPU

  supporting VHE, the EL2 MMU being off, and VHE not being disabled by

  any other means (command line option, for example).



Any other value of r0/x0 triggers a hypervisor-specific handling,

which is not documented here.

arch/arm64/include/asm/assembler.h

+27 −4
Original line number Diff line number Diff line
@@ -359,6 +359,20 @@ alternative_cb_end 
	bfi	\valreg, \t1sz, #TCR_T1SZ_OFFSET, #TCR_TxSZ_WIDTH

	.endm



/*

 * idmap_get_t0sz - get the T0SZ value needed to cover the ID map

 *

 * Calculate the maximum allowed value for TCR_EL1.T0SZ so that the

 * entire ID map region can be mapped. As T0SZ == (64 - #bits used),

 * this number conveniently equals the number of leading zeroes in

 * the physical address of _end.

 */

	.macro	idmap_get_t0sz, reg

	adrp	\reg, _end

	orr	\reg, \reg, #(1 << VA_BITS_MIN) - 1

	clz	\reg, \reg

	.endm



/*

 * tcr_compute_pa_size - set TCR.(I)PS to the highest supported

 * ID_AA64MMFR0_EL1.PARange value
@@ -465,6 +479,18 @@ alternative_endif 
	_cond_uaccess_extable .Licache_op\@, \fixup

	.endm



/*

 * load_ttbr1 - install @pgtbl as a TTBR1 page table

 * pgtbl preserved

 * tmp1/tmp2 clobbered, either may overlap with pgtbl

 */

	.macro		load_ttbr1, pgtbl, tmp1, tmp2

	phys_to_ttbr	\tmp1, \pgtbl

	offset_ttbr1 	\tmp1, \tmp2

	msr		ttbr1_el1, \tmp1

	isb

	.endm



/*

 * To prevent the possibility of old and new partial table walks being visible

 * in the tlb, switch the ttbr to a zero page when we invalidate the old
@@ -478,10 +504,7 @@ alternative_endif 
	isb

	tlbi	vmalle1

	dsb	nsh

	phys_to_ttbr \tmp, \page_table

	offset_ttbr1 \tmp, \tmp2

	msr	ttbr1_el1, \tmp

	isb

	load_ttbr1 \page_table, \tmp, \tmp2

	.endm



/*

arch/arm64/include/asm/cpufeature.h

+3 −0
Original line number Diff line number Diff line
@@ -908,7 +908,10 @@ static inline unsigned int get_vmid_bits(u64 mmfr1) 
}



extern struct arm64_ftr_override id_aa64mmfr1_override;

extern struct arm64_ftr_override id_aa64pfr0_override;

extern struct arm64_ftr_override id_aa64pfr1_override;

extern struct arm64_ftr_override id_aa64zfr0_override;

extern struct arm64_ftr_override id_aa64smfr0_override;

extern struct arm64_ftr_override id_aa64isar1_override;

extern struct arm64_ftr_override id_aa64isar2_override;

arch/arm64/include/asm/el2_setup.h

+0 −60
Original line number Diff line number Diff line
@@ -129,64 +129,6 @@ 
	msr	cptr_el2, x0			// Disable copro. traps to EL2

.endm



/* SVE register access */

.macro __init_el2_nvhe_sve

	mrs	x1, id_aa64pfr0_el1

	ubfx	x1, x1, #ID_AA64PFR0_SVE_SHIFT, #4

	cbz	x1, .Lskip_sve_\@



	bic	x0, x0, #CPTR_EL2_TZ		// Also disable SVE traps

	msr	cptr_el2, x0			// Disable copro. traps to EL2

	isb

	mov	x1, #ZCR_ELx_LEN_MASK		// SVE: Enable full vector

	msr_s	SYS_ZCR_EL2, x1			// length for EL1.

.Lskip_sve_\@:

.endm



/* SME register access and priority mapping */

.macro __init_el2_nvhe_sme

	mrs	x1, id_aa64pfr1_el1

	ubfx	x1, x1, #ID_AA64PFR1_SME_SHIFT, #4

	cbz	x1, .Lskip_sme_\@



	bic	x0, x0, #CPTR_EL2_TSM		// Also disable SME traps

	msr	cptr_el2, x0			// Disable copro. traps to EL2

	isb



	mrs	x1, sctlr_el2

	orr	x1, x1, #SCTLR_ELx_ENTP2	// Disable TPIDR2 traps

	msr	sctlr_el2, x1

	isb



	mov	x1, #0				// SMCR controls



	mrs_s	x2, SYS_ID_AA64SMFR0_EL1

	ubfx	x2, x2, #ID_AA64SMFR0_EL1_FA64_SHIFT, #1 // Full FP in SM?

	cbz	x2, .Lskip_sme_fa64_\@



	orr	x1, x1, SMCR_ELx_FA64_MASK

.Lskip_sme_fa64_\@:



	orr	x1, x1, #SMCR_ELx_LEN_MASK	// Enable full SME vector

	msr_s	SYS_SMCR_EL2, x1		// length for EL1.



	mrs_s	x1, SYS_SMIDR_EL1		// Priority mapping supported?

	ubfx    x1, x1, #SMIDR_EL1_SMPS_SHIFT, #1

	cbz     x1, .Lskip_sme_\@



	msr_s	SYS_SMPRIMAP_EL2, xzr		// Make all priorities equal



	mrs	x1, id_aa64mmfr1_el1		// HCRX_EL2 present?

	ubfx	x1, x1, #ID_AA64MMFR1_HCX_SHIFT, #4

	cbz	x1, .Lskip_sme_\@



	mrs_s	x1, SYS_HCRX_EL2

	orr	x1, x1, #HCRX_EL2_SMPME_MASK	// Enable priority mapping

	msr_s	SYS_HCRX_EL2, x1



.Lskip_sme_\@:

.endm



/* Disable any fine grained traps */

.macro __init_el2_fgt

	mrs	x1, id_aa64mmfr0_el1
@@ -250,8 +192,6 @@ 
	__init_el2_hstr

	__init_el2_nvhe_idregs

	__init_el2_nvhe_cptr

	__init_el2_nvhe_sve

	__init_el2_nvhe_sme

	__init_el2_fgt

	__init_el2_nvhe_prepare_eret

.endm