Commit f944d061 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2021-03-26' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "As expected last week things were overly quiet so this week things
  seem to have caught up. It still isn't too major.

  msm and amdgpu lead the size here, the msm fixes are pretty varied
  across the driver, the amdgpu one is mostly the S0ix fixes with some
  other minor ones. Otherwise there are a few i915 fixes and one each
  for nouveau, etnaviv and rcar-du.

  msm:
   - pll fixes
   - shutdown hook fix
   - runtime resume fix
   - clear_oob fix
   - kms locking fix
   - display aux retry fix

  rcar-du:
   - warn_on in encoder init fix

  etnaviv:
   - Use FOLL_FORCE and FOLL_LONGTERM

  i915:
   - DisplayPort LTTPR fixes around link training and limiting it
     according to supported spec version.
   - Fix enabled_planes bitmask to really represent only logically
     enabled planes.
   - Fix DSS CTL registers for ICL DSI transcoders
   - Fix the GT fence revocation runtime PM logic.

  nouveau:
   - cursor size regression fix

  amdgpu:
   - S0ix fixes
   - Add PCI ID
   - Polaris PCIe DPM fix
   - Display fix for high refresh rate monitors"

* tag 'drm-fixes-2021-03-26' of git://anongit.freedesktop.org/drm/drm: (37 commits)
  drm/nouveau/kms/nve4-nv108: Limit cursors to 128x128
  drm/i915: Fix the GT fence revocation runtime PM logic
  drm/amdgpu/display: restore AUX_DPHY_TX_CONTROL for DCN2.x
  drm/amdgpu: Add additional Sienna Cichlid PCI ID
  drm/amd/pm: workaround for audio noise issue
  drm/i915/dsc: fix DSS CTL register usage for ICL DSI transcoders
  drm/i915: Fix enabled_planes bitmask
  drm/i915: Disable LTTPR support when the LTTPR rev < 1.4
  drm/i915: Disable LTTPR support when the DPCD rev < 1.4
  drm/i915/ilk-glk: Fix link training on links with LTTPRs
  drm/msm/disp/dpu1: icc path needs to be set before dpu runtime resume
  drm/amdgpu: skip kfd suspend/resume for S0ix
  drm/amdgpu: drop S0ix checks around CG/PG in suspend
  drm/amdgpu: skip CG/PG for gfx during S0ix
  drm/amdgpu: update comments about s0ix suspend/resume
  drm/amdgpu/swsmu: skip gfx cgpg on s0ix suspend
  drm/amdgpu: re-enable suspend phase 2 for S0ix
  drm/amdgpu: move s0ix check into amdgpu_device_ip_suspend_phase2 (v3)
  drm/amdgpu: clean up non-DC suspend/resume handling
  drm/amdgpu: don't evict vram on APUs for suspend to ram (v4)
  ...
parents 57a90062 09d78dde

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+3 −7
Original line number Diff line number Diff line
@@ -1007,13 +1007,9 @@ struct amdgpu_device { 


	/* s3/s4 mask */

	bool                            in_suspend;

	bool				in_hibernate;



	/*

	 * The combination flag in_poweroff_reboot_com used to identify the poweroff

	 * and reboot opt in the s0i3 system-wide suspend.

	 */

	bool 				in_poweroff_reboot_com;

	bool				in_s3;

	bool				in_s4;

	bool				in_s0ix;



	atomic_t 			in_gpu_reset;

	enum pp_mp1_state               mp1_state;

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+34 −98
Original line number Diff line number Diff line
@@ -2371,6 +2371,10 @@ static int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 
		i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;

		if (!adev->ip_blocks[i].status.late_initialized)

			continue;

		/* skip CG for GFX on S0ix */

		if (adev->in_s0ix &&

		    adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX)

			continue;

		/* skip CG for VCE/UVD, it's handled specially */

		if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&

		    adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
@@ -2402,6 +2406,10 @@ static int amdgpu_device_set_pg_state(struct amdgpu_device *adev, enum amd_power 
		i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;

		if (!adev->ip_blocks[i].status.late_initialized)

			continue;

		/* skip PG for GFX on S0ix */

		if (adev->in_s0ix &&

		    adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX)

			continue;

		/* skip CG for VCE/UVD, it's handled specially */

		if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&

		    adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
@@ -2678,11 +2686,8 @@ static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev) 
{

	int i, r;



	if (adev->in_poweroff_reboot_com ||

	    !amdgpu_acpi_is_s0ix_supported(adev) || amdgpu_in_reset(adev)) {

	amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);

	amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);

	}



	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {

		if (!adev->ip_blocks[i].status.valid)
@@ -2722,6 +2727,9 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev) 
{

	int i, r;



	if (adev->in_s0ix)

		amdgpu_gfx_state_change_set(adev, sGpuChangeState_D3Entry);



	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {

		if (!adev->ip_blocks[i].status.valid)

			continue;
@@ -2734,6 +2742,17 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev) 
			adev->ip_blocks[i].status.hw = false;

			continue;

		}



		/* skip suspend of gfx and psp for S0ix

		 * gfx is in gfxoff state, so on resume it will exit gfxoff just

		 * like at runtime. PSP is also part of the always on hardware

		 * so no need to suspend it.

		 */

		if (adev->in_s0ix &&

		    (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP ||

		     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX))

			continue;



		/* XXX handle errors */

		r = adev->ip_blocks[i].version->funcs->suspend(adev);

		/* XXX handle errors */
@@ -3673,14 +3692,9 @@ void amdgpu_device_fini(struct amdgpu_device *adev) 
 */

int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)

{

	struct amdgpu_device *adev;

	struct drm_crtc *crtc;

	struct drm_connector *connector;

	struct drm_connector_list_iter iter;

	struct amdgpu_device *adev = drm_to_adev(dev);

	int r;



	adev = drm_to_adev(dev);



	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)

		return 0;
@@ -3692,49 +3706,11 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon) 


	cancel_delayed_work_sync(&adev->delayed_init_work);



	if (!amdgpu_device_has_dc_support(adev)) {

		/* turn off display hw */

		drm_modeset_lock_all(dev);

		drm_connector_list_iter_begin(dev, &iter);

		drm_for_each_connector_iter(connector, &iter)

			drm_helper_connector_dpms(connector,

						  DRM_MODE_DPMS_OFF);

		drm_connector_list_iter_end(&iter);

		drm_modeset_unlock_all(dev);

			/* unpin the front buffers and cursors */

		list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {

			struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

			struct drm_framebuffer *fb = crtc->primary->fb;

			struct amdgpu_bo *robj;



			if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {

				struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);

				r = amdgpu_bo_reserve(aobj, true);

				if (r == 0) {

					amdgpu_bo_unpin(aobj);

					amdgpu_bo_unreserve(aobj);

				}

			}



			if (fb == NULL || fb->obj[0] == NULL) {

				continue;

			}

			robj = gem_to_amdgpu_bo(fb->obj[0]);

			/* don't unpin kernel fb objects */

			if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {

				r = amdgpu_bo_reserve(robj, true);

				if (r == 0) {

					amdgpu_bo_unpin(robj);

					amdgpu_bo_unreserve(robj);

				}

			}

		}

	}



	amdgpu_ras_suspend(adev);



	r = amdgpu_device_ip_suspend_phase1(adev);



	if (!adev->in_s0ix)

		amdgpu_amdkfd_suspend(adev, adev->in_runpm);



	/* evict vram memory */
@@ -3742,11 +3718,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon) 


	amdgpu_fence_driver_suspend(adev);



	if (adev->in_poweroff_reboot_com ||

	    !amdgpu_acpi_is_s0ix_supported(adev) || amdgpu_in_reset(adev))

	r = amdgpu_device_ip_suspend_phase2(adev);

	else

		amdgpu_gfx_state_change_set(adev, sGpuChangeState_D3Entry);

	/* evict remaining vram memory

	 * This second call to evict vram is to evict the gart page table

	 * using the CPU.
@@ -3768,16 +3740,13 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon) 
 */

int amdgpu_device_resume(struct drm_device *dev, bool fbcon)

{

	struct drm_connector *connector;

	struct drm_connector_list_iter iter;

	struct amdgpu_device *adev = drm_to_adev(dev);

	struct drm_crtc *crtc;

	int r = 0;



	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)

		return 0;



	if (amdgpu_acpi_is_s0ix_supported(adev))

	if (adev->in_s0ix)

		amdgpu_gfx_state_change_set(adev, sGpuChangeState_D0Entry);



	/* post card */
@@ -3802,50 +3771,17 @@ int amdgpu_device_resume(struct drm_device *dev, bool fbcon) 
	queue_delayed_work(system_wq, &adev->delayed_init_work,

			   msecs_to_jiffies(AMDGPU_RESUME_MS));



	if (!amdgpu_device_has_dc_support(adev)) {

		/* pin cursors */

		list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {

			struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);



			if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {

				struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);

				r = amdgpu_bo_reserve(aobj, true);

				if (r == 0) {

					r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);

					if (r != 0)

						dev_err(adev->dev, "Failed to pin cursor BO (%d)\n", r);

					amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);

					amdgpu_bo_unreserve(aobj);

				}

			}

		}

	}

	if (!adev->in_s0ix) {

		r = amdgpu_amdkfd_resume(adev, adev->in_runpm);

		if (r)

			return r;

	}



	/* Make sure IB tests flushed */

	flush_delayed_work(&adev->delayed_init_work);



	/* blat the mode back in */

	if (fbcon) {

		if (!amdgpu_device_has_dc_support(adev)) {

			/* pre DCE11 */

			drm_helper_resume_force_mode(dev);



			/* turn on display hw */

			drm_modeset_lock_all(dev);



			drm_connector_list_iter_begin(dev, &iter);

			drm_for_each_connector_iter(connector, &iter)

				drm_helper_connector_dpms(connector,

							  DRM_MODE_DPMS_ON);

			drm_connector_list_iter_end(&iter);



			drm_modeset_unlock_all(dev);

		}

	if (fbcon)

		amdgpu_fbdev_set_suspend(adev, 0);

	}



	drm_kms_helper_poll_enable(dev);

drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

+89 −0
Original line number Diff line number Diff line
@@ -1310,3 +1310,92 @@ bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc, 
	return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,

						  stime, etime, mode);

}



int amdgpu_display_suspend_helper(struct amdgpu_device *adev)

{

	struct drm_device *dev = adev_to_drm(adev);

	struct drm_crtc *crtc;

	struct drm_connector *connector;

	struct drm_connector_list_iter iter;

	int r;



	/* turn off display hw */

	drm_modeset_lock_all(dev);

	drm_connector_list_iter_begin(dev, &iter);

	drm_for_each_connector_iter(connector, &iter)

		drm_helper_connector_dpms(connector,

					  DRM_MODE_DPMS_OFF);

	drm_connector_list_iter_end(&iter);

	drm_modeset_unlock_all(dev);

	/* unpin the front buffers and cursors */

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {

		struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

		struct drm_framebuffer *fb = crtc->primary->fb;

		struct amdgpu_bo *robj;



		if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {

			struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);

			r = amdgpu_bo_reserve(aobj, true);

			if (r == 0) {

				amdgpu_bo_unpin(aobj);

				amdgpu_bo_unreserve(aobj);

			}

		}



		if (fb == NULL || fb->obj[0] == NULL) {

			continue;

		}

		robj = gem_to_amdgpu_bo(fb->obj[0]);

		/* don't unpin kernel fb objects */

		if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {

			r = amdgpu_bo_reserve(robj, true);

			if (r == 0) {

				amdgpu_bo_unpin(robj);

				amdgpu_bo_unreserve(robj);

			}

		}

	}

	return r;

}



int amdgpu_display_resume_helper(struct amdgpu_device *adev)

{

	struct drm_device *dev = adev_to_drm(adev);

	struct drm_connector *connector;

	struct drm_connector_list_iter iter;

	struct drm_crtc *crtc;

	int r;



	/* pin cursors */

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {

		struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);



		if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {

			struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);

			r = amdgpu_bo_reserve(aobj, true);

			if (r == 0) {

				r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);

				if (r != 0)

					dev_err(adev->dev, "Failed to pin cursor BO (%d)\n", r);

				amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);

				amdgpu_bo_unreserve(aobj);

			}

		}

	}



	drm_helper_resume_force_mode(dev);



	/* turn on display hw */

	drm_modeset_lock_all(dev);



	drm_connector_list_iter_begin(dev, &iter);

	drm_for_each_connector_iter(connector, &iter)

		drm_helper_connector_dpms(connector,

					  DRM_MODE_DPMS_ON);

	drm_connector_list_iter_end(&iter);



	drm_modeset_unlock_all(dev);



	return 0;

}

drivers/gpu/drm/amd/amdgpu/amdgpu_display.h

+3 −0
Original line number Diff line number Diff line
@@ -47,4 +47,7 @@ amdgpu_display_user_framebuffer_create(struct drm_device *dev, 
const struct drm_format_info *

amdgpu_lookup_format_info(u32 format, uint64_t modifier);



int amdgpu_display_suspend_helper(struct amdgpu_device *adev);

int amdgpu_display_resume_helper(struct amdgpu_device *adev);



#endif

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+19 −12
Original line number Diff line number Diff line
@@ -1107,6 +1107,7 @@ static const struct pci_device_id pciidlist[] = { 
	{0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},

	{0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},

	{0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},

	{0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},

	{0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},



	/* Van Gogh */
@@ -1274,24 +1275,35 @@ amdgpu_pci_shutdown(struct pci_dev *pdev) 
	 */

	if (!amdgpu_passthrough(adev))

		adev->mp1_state = PP_MP1_STATE_UNLOAD;

	adev->in_poweroff_reboot_com = true;

	amdgpu_device_ip_suspend(adev);

	adev->in_poweroff_reboot_com = false;

	adev->mp1_state = PP_MP1_STATE_NONE;

}



static int amdgpu_pmops_suspend(struct device *dev)

{

	struct drm_device *drm_dev = dev_get_drvdata(dev);

	struct amdgpu_device *adev = drm_to_adev(drm_dev);

	int r;



	return amdgpu_device_suspend(drm_dev, true);

	if (amdgpu_acpi_is_s0ix_supported(adev))

		adev->in_s0ix = true;

	adev->in_s3 = true;

	r = amdgpu_device_suspend(drm_dev, true);

	adev->in_s3 = false;



	return r;

}



static int amdgpu_pmops_resume(struct device *dev)

{

	struct drm_device *drm_dev = dev_get_drvdata(dev);

	struct amdgpu_device *adev = drm_to_adev(drm_dev);

	int r;



	return amdgpu_device_resume(drm_dev, true);

	r = amdgpu_device_resume(drm_dev, true);

	if (amdgpu_acpi_is_s0ix_supported(adev))

		adev->in_s0ix = false;

	return r;

}



static int amdgpu_pmops_freeze(struct device *dev)
@@ -1300,9 +1312,9 @@ static int amdgpu_pmops_freeze(struct device *dev) 
	struct amdgpu_device *adev = drm_to_adev(drm_dev);

	int r;



	adev->in_hibernate = true;

	adev->in_s4 = true;

	r = amdgpu_device_suspend(drm_dev, true);

	adev->in_hibernate = false;

	adev->in_s4 = false;

	if (r)

		return r;

	return amdgpu_asic_reset(adev);
@@ -1318,13 +1330,8 @@ static int amdgpu_pmops_thaw(struct device *dev) 
static int amdgpu_pmops_poweroff(struct device *dev)

{

	struct drm_device *drm_dev = dev_get_drvdata(dev);

	struct amdgpu_device *adev = drm_to_adev(drm_dev);

	int r;



	adev->in_poweroff_reboot_com = true;

	r =  amdgpu_device_suspend(drm_dev, true);

	adev->in_poweroff_reboot_com = false;

	return r;

	return amdgpu_device_suspend(drm_dev, true);

}



static int amdgpu_pmops_restore(struct device *dev)