Commit f92d9ee3 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/host-xgene' into next 

* pci/host-xgene:
  arm64: dts: Add APM X-Gene PCIe device tree nodes
  PCI: xgene: Add APM X-Gene PCIe driver

Conflicts:
	drivers/pci/host/Kconfig
	drivers/pci/host/Makefile
parents 55dd4175 767ebaff

Documentation/devicetree/bindings/pci/xgene-pci.txt

0 → 100644
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* AppliedMicro X-Gene PCIe interface



Required properties:

- device_type: set to "pci"

- compatible: should contain "apm,xgene-pcie" to identify the core.

- reg: A list of physical base address and length for each set of controller

       registers. Must contain an entry for each entry in the reg-names

       property.

- reg-names: Must include the following entries:

  "csr": controller configuration registers.

  "cfg": pcie configuration space registers.

- #address-cells: set to <3>

- #size-cells: set to <2>

- ranges: ranges for the outbound memory, I/O regions.

- dma-ranges: ranges for the inbound memory regions.

- #interrupt-cells: set to <1>

- interrupt-map-mask and interrupt-map: standard PCI properties

	to define the mapping of the PCIe interface to interrupt

	numbers.

- clocks: from common clock binding: handle to pci clock.



Optional properties:

- status: Either "ok" or "disabled".

- dma-coherent: Present if dma operations are coherent



Example:



SoC specific DT Entry:



	pcie0: pcie@1f2b0000 {

		status = "disabled";

		device_type = "pci";

		compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";

		#interrupt-cells = <1>;

		#size-cells = <2>;

		#address-cells = <3>;

		reg = < 0x00 0x1f2b0000 0x0 0x00010000   /* Controller registers */

			0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */

		reg-names = "csr", "cfg";

		ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000   /* io */

			  0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */

		dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000

			      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;

		interrupt-map-mask = <0x0 0x0 0x0 0x7>;

		interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1

				 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1

				 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1

				 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;

		dma-coherent;

		clocks = <&pcie0clk 0>;

	};





Board specific DT Entry:

	&pcie0 {

		status = "ok";

	};

MAINTAINERS

+8 −0
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@@ -6868,6 +6868,14 @@ F: include/linux/pci* 
F:	arch/x86/pci/

F:	arch/x86/kernel/quirks.c



PCI DRIVER FOR APPLIEDMICRO XGENE

M:	Tanmay Inamdar <tinamdar@apm.com>

L:	linux-pci@vger.kernel.org

L:	linux-arm-kernel@lists.infradead.org

S:	Maintained

F:	Documentation/devicetree/bindings/pci/xgene-pci.txt

F:	drivers/pci/host/pci-xgene.c



PCI DRIVER FOR IMX6

M:	Richard Zhu <r65037@freescale.com>

M:	Lucas Stach <l.stach@pengutronix.de>

arch/arm64/boot/dts/apm-mustang.dts

+8 −0
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@@ -25,6 +25,14 @@ 
	};

};



&pcie0clk {

	status = "ok";

};



&pcie0 {

	status = "ok";

};



&serial0 {

	status = "ok";

};

arch/arm64/boot/dts/apm-storm.dtsi

+165 −0
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@@ -269,6 +269,171 @@ 
				enable-mask = <0x2>;

				clock-output-names = "rtcclk";

			};



			pcie0clk: pcie0clk@1f2bc000 {

				status = "disabled";

				compatible = "apm,xgene-device-clock";

				#clock-cells = <1>;

				clocks = <&socplldiv2 0>;

				reg = <0x0 0x1f2bc000 0x0 0x1000>;

				reg-names = "csr-reg";

				clock-output-names = "pcie0clk";

			};



			pcie1clk: pcie1clk@1f2cc000 {

				status = "disabled";

				compatible = "apm,xgene-device-clock";

				#clock-cells = <1>;

				clocks = <&socplldiv2 0>;

				reg = <0x0 0x1f2cc000 0x0 0x1000>;

				reg-names = "csr-reg";

				clock-output-names = "pcie1clk";

			};



			pcie2clk: pcie2clk@1f2dc000 {

				status = "disabled";

				compatible = "apm,xgene-device-clock";

				#clock-cells = <1>;

				clocks = <&socplldiv2 0>;

				reg = <0x0 0x1f2dc000 0x0 0x1000>;

				reg-names = "csr-reg";

				clock-output-names = "pcie2clk";

			};



			pcie3clk: pcie3clk@1f50c000 {

				status = "disabled";

				compatible = "apm,xgene-device-clock";

				#clock-cells = <1>;

				clocks = <&socplldiv2 0>;

				reg = <0x0 0x1f50c000 0x0 0x1000>;

				reg-names = "csr-reg";

				clock-output-names = "pcie3clk";

			};



			pcie4clk: pcie4clk@1f51c000 {

				status = "disabled";

				compatible = "apm,xgene-device-clock";

				#clock-cells = <1>;

				clocks = <&socplldiv2 0>;

				reg = <0x0 0x1f51c000 0x0 0x1000>;

				reg-names = "csr-reg";

				clock-output-names = "pcie4clk";

			};

		};



		pcie0: pcie@1f2b0000 {

			status = "disabled";

			device_type = "pci";

			compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";

			#interrupt-cells = <1>;

			#size-cells = <2>;

			#address-cells = <3>;

			reg = < 0x00 0x1f2b0000 0x0 0x00010000   /* Controller registers */

				0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */

			reg-names = "csr", "cfg";

			ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000   /* io */

				  0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */

			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000

				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;

			interrupt-map-mask = <0x0 0x0 0x0 0x7>;

			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1

					 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1

					 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1

					 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;

			dma-coherent;

			clocks = <&pcie0clk 0>;

		};



		pcie1: pcie@1f2c0000 {

			status = "disabled";

			device_type = "pci";

			compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";

			#interrupt-cells = <1>;

			#size-cells = <2>;

			#address-cells = <3>;

			reg = < 0x00 0x1f2c0000 0x0 0x00010000   /* Controller registers */

				0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */

			reg-names = "csr", "cfg";

			ranges = <0x01000000 0x0 0x00000000 0xd0 0x10000000 0x00 0x00010000   /* io  */

				  0x02000000 0x0 0x80000000 0xd1 0x80000000 0x00 0x80000000>; /* mem */

			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000

				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;

			interrupt-map-mask = <0x0 0x0 0x0 0x7>;

			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x1

					 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x1

					 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x1

					 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>;

			dma-coherent;

			clocks = <&pcie1clk 0>;

		};



		pcie2: pcie@1f2d0000 {

			status = "disabled";

			device_type = "pci";

			compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";

			#interrupt-cells = <1>;

			#size-cells = <2>;

			#address-cells = <3>;

			reg =  < 0x00 0x1f2d0000 0x0 0x00010000   /* Controller registers */

				 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */

			reg-names = "csr", "cfg";

			ranges = <0x01000000 0x0 0x00000000 0x90 0x10000000 0x0 0x00010000   /* io  */

				  0x02000000 0x0 0x80000000 0x91 0x80000000 0x0 0x80000000>; /* mem */

			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000

				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;

			interrupt-map-mask = <0x0 0x0 0x0 0x7>;

			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x1

					 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x1

					 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x1

					 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>;

			dma-coherent;

			clocks = <&pcie2clk 0>;

		};



		pcie3: pcie@1f500000 {

			status = "disabled";

			device_type = "pci";

			compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";

			#interrupt-cells = <1>;

			#size-cells = <2>;

			#address-cells = <3>;

			reg = < 0x00 0x1f500000 0x0 0x00010000   /* Controller registers */

				0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */

			reg-names = "csr", "cfg";

			ranges = <0x01000000 0x0 0x00000000 0xa0 0x10000000 0x0 0x00010000   /* io   */

				  0x02000000 0x0 0x80000000 0xa1 0x80000000 0x0 0x80000000>; /* mem  */

			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000

				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;

			interrupt-map-mask = <0x0 0x0 0x0 0x7>;

			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x1

					 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x1

					 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x1

					 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>;

			dma-coherent;

			clocks = <&pcie3clk 0>;

		};



		pcie4: pcie@1f510000 {

			status = "disabled";

			device_type = "pci";

			compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";

			#interrupt-cells = <1>;

			#size-cells = <2>;

			#address-cells = <3>;

			reg = < 0x00 0x1f510000 0x0 0x00010000   /* Controller registers */

				0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */

			reg-names = "csr", "cfg";

			ranges = <0x01000000 0x0 0x00000000 0xc0 0x10000000 0x0 0x00010000   /* io  */

				  0x02000000 0x0 0x80000000 0xc1 0x80000000 0x0 0x80000000>; /* mem */

			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000

				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;

			interrupt-map-mask = <0x0 0x0 0x0 0x7>;

			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x1

					 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x1

					 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x1

					 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x1>;

			dma-coherent;

			clocks = <&pcie4clk 0>;

		};



		serial0: serial@1c020000 {

drivers/pci/host/Kconfig

+10 −1
Original line number Diff line number Diff line
@@ -63,7 +63,6 @@ config PCIE_SPEAR13XX 
	help

	  Say Y here if you want PCIe support on SPEAr13XX SoCs.





config PCI_KEYSTONE

	bool "TI Keystone PCIe controller"

	depends on ARCH_KEYSTONE
@@ -82,4 +81,14 @@ config PCIE_XILINX 
	  Say 'Y' here if you want kernel to support the Xilinx AXI PCIe

	  Host Bridge driver.



config PCI_XGENE

	bool "X-Gene PCIe controller"

	depends on ARCH_XGENE

	depends on OF

	select PCIEPORTBUS

	help

	  Say Y here if you want internal PCI support on APM X-Gene SoC.

	  There are 5 internal PCIe ports available. Each port is GEN3 capable

	  and have varied lanes from x1 to x8.



endmenu