Commit f8f96b17 authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: init rlcg_reg_access_ctrl for gfx10 



Initialize all the register offsets that will be
used in rlcg indirect reg access path for gfx10
in sw_init phase

Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarZhou, Peng Ju <PengJu.Zhou@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4819732f

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+34 −4
Original line number Diff line number Diff line
@@ -4411,6 +4411,30 @@ static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev) 
			(void **)&adev->gfx.rlc.cp_table_ptr);

}



static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)

{

	struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;



	reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl;

	reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);

	reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1);

	reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2);

	reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3);

	reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL);

	reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX);

	switch (adev->ip_versions[GC_HWIP][0]) {

		case IP_VERSION(10, 3, 0):

			reg_access_ctrl->spare_int =

				SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid);

			break;

		default:

			reg_access_ctrl->spare_int =

				SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT);

			break;

	}

	adev->gfx.rlc.rlcg_reg_access_supported = true;

}



static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)

{

	const struct cs_section_def *cs_data;
@@ -4431,6 +4455,8 @@ static int gfx_v10_0_rlc_init(struct amdgpu_device *adev) 
	if (adev->gfx.rlc.funcs->update_spm_vmid)

		adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);



	gfx_v10_0_init_rlcg_reg_access_ctrl(adev);



	return 0;

}
@@ -4828,11 +4854,15 @@ static int gfx_v10_0_sw_init(void *handle) 
	if (r)

		return r;



	r = gfx_v10_0_rlc_init(adev);

	if (adev->gfx.rlc.funcs) {

		if (adev->gfx.rlc.funcs->init) {

			r = adev->gfx.rlc.funcs->init(adev);

			if (r) {

		DRM_ERROR("Failed to init rlc BOs!\n");

				dev_err(adev->dev, "Failed to init rlc BOs!\n");

				return r;

			}

		}

	}



	r = gfx_v10_0_mec_init(adev);

	if (r) {