Commit f8c9dd2b authored Dec 11, 2020 by Sowjanya Komatineni Committed by Mauro Carvalho Chehab Jan 04, 2021

media: dt-bindings: tegra: Update csi data-lanes to maximum 8 lanes



Tegra VI/CSI hardware don't have native 8 lane CSI RX port.

But x8 capture can be supported by using consecutive x4 ports
simultaneously with HDMI-to-CSI bridges where source image is split
on to two x4 ports.

This patch updates dt-bindings for csi endpoint data-lane property
with maximum of 8 lanes.

Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

parent 8f81888b

Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt

+2 −2

Original line number	Diff line number	Diff line
		@@ -111,8 +111,8 @@ of the following host1x client modules:

		endpoint (required node)
		Required properties:
		- data-lanes: an array of data lane from 1 to 4. Valid array
		lengths are 1/2/4.
		- data-lanes: an array of data lane from 1 to 8. Valid array
		lengths are 1/2/4/8.
		- remote-endpoint: phandle to sensor 'endpoint' node.

		port@1 (required node)