Unverified Commit f8ab733c authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
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!6294 [sync] PR-6177: arm64/mpam: Not allowed setting 0 to cache portion bit mask 

Merge Pull Request from: @openeuler-sync-bot 
 

Origin pull request: 
https://gitee.com/openeuler/kernel/pulls/6177 
 
PR sync from: Zeng Heng <zengheng4@huawei.com>
https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/message/GWGQZLHDINI7Q4NYHYZMU45W6HHZFI7J/ 
 
https://gitee.com/openeuler/kernel/issues/I9H4YE 
 
Link:https://gitee.com/openeuler/kernel/pulls/6294

 

Reviewed-by: default avatarWei Li <liwei391@huawei.com>
Signed-off-by: default avatarJialin Zhang <zhangjialin11@huawei.com>
parents d7f31fdb 54617104

arch/arm64/kernel/mpam/mpam_resctrl.c

+5 −0
Original line number Diff line number Diff line
@@ -320,6 +320,11 @@ parse_cache(char *buf, struct resctrl_resource *r, 
		return -EINVAL;

	}



	if (type == SCHEMA_COMM && data == 0) {

		rdt_last_cmd_puts("No allowed CPBM to be set to 0\n");

		return -EINVAL;

	}



	cfg->new_ctrl[type] = data;

	cfg->ctrl_updated[type] = true;

	cfg->have_new_ctrl = true;