Unverified Commit f8953043 authored by Shengjiu Wang's avatar Shengjiu Wang Committed by Mark Brown
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ASoC: fsl_asrc: Set ASR76K and ASR56K based on processing clock 



The processing clock is different for platforms, so it is better
to set ASR76K and ASR56K based on processing clock, rather than
hard coding the value for them.

Signed-off-by: default avatarShengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: default avatarMihai Serban <mihai.serban@nxp.com>
Link: https://lore.kernel.org/r/1589278979-31008-1-git-send-email-shengjiu.wang@nxp.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 0e0e10fd

sound/soc/fsl/fsl_asrc.c

+10 −5
Original line number Diff line number Diff line
@@ -858,6 +858,8 @@ static const struct regmap_config fsl_asrc_regmap_config = { 
 */

static int fsl_asrc_init(struct fsl_asrc *asrc)

{

	unsigned long ipg_rate;



	/* Halt ASRC internal FP when input FIFO needs data for pair A, B, C */

	regmap_write(asrc->regmap, REG_ASRCTR, ASRCTR_ASRCEN);
@@ -875,11 +877,14 @@ static int fsl_asrc_init(struct fsl_asrc *asrc) 
	regmap_update_bits(asrc->regmap, REG_ASRTFR1,

			   ASRTFR1_TF_BASE_MASK, ASRTFR1_TF_BASE(0xfc));



	/* Set the processing clock for 76KHz to 133M */

	regmap_write(asrc->regmap, REG_ASR76K, 0x06D6);



	/* Set the processing clock for 56KHz to 133M */

	return regmap_write(asrc->regmap, REG_ASR56K, 0x0947);

	/*

	 * Set the period of the 76KHz and 56KHz sampling clocks based on

	 * the ASRC processing clock.

	 * On iMX6, ipg_clk = 133MHz, REG_ASR76K = 0x06D6, REG_ASR56K = 0x0947

	 */

	ipg_rate = clk_get_rate(asrc->ipg_clk);

	regmap_write(asrc->regmap, REG_ASR76K, ipg_rate / 76000);

	return regmap_write(asrc->regmap, REG_ASR56K, ipg_rate / 56000);

}



/**