Unverified Commit f8950430 authored by Mark Brown's avatar Mark Brown
Browse files

spi: Stacked/parallel memories bindings 

Merge series from Miquel Raynal <miquel.raynal@bootlin.com>:

DT bindings for stacked and parallel flash/memory devices.

base-commit: e783362e
parents c5a3106a eba53685

Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml

+2 −1
Original line number Diff line number Diff line
@@ -47,7 +47,8 @@ properties: 
      identified by the JEDEC READ ID opcode (0x9F).



  reg:

    maxItems: 1

    minItems: 1

    maxItems: 2



  spi-max-frequency: true

  spi-rx-bus-width: true

Documentation/devicetree/bindings/spi/spi-controller.yaml

+7 −0
Original line number Diff line number Diff line
@@ -139,4 +139,11 @@ examples: 
            spi-max-frequency = <100000>;

            reg = <1>;

        };



        flash@2 {

          compatible = "jedec,spi-nor";

          spi-max-frequency = <50000000>;

          reg = <2>, <3>;

          stacked-memories = /bits/ 64 <0x10000000 0x10000000>;

        };

    };

Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml

+25 −0
Original line number Diff line number Diff line
@@ -83,6 +83,31 @@ properties: 
    description:

      Delay, in microseconds, after a write transfer.



  stacked-memories:

    description: Several SPI memories can be wired in stacked mode.

      This basically means that either a device features several chip

      selects, or that different devices must be seen as a single

      bigger chip. This basically doubles (or more) the total address

      space with only a single additional wire, while still needing

      to repeat the commands when crossing a chip boundary. The size of

      each chip should be provided as members of the array.

    $ref: /schemas/types.yaml#/definitions/uint64-array

    minItems: 2

    maxItems: 4



  parallel-memories:

    description: Several SPI memories can be wired in parallel mode.

      The devices are physically on a different buses but will always

      act synchronously as each data word is spread across the

      different memories (eg. even bits are stored in one memory, odd

      bits in the other). This basically doubles the address space and

      the throughput while greatly complexifying the wiring because as

      many busses as devices must be wired. The size of each chip should

      be provided as members of the array.

    $ref: /schemas/types.yaml#/definitions/uint64-array

    minItems: 2

    maxItems: 4



# The controller specific properties go here.

allOf:

  - $ref: cdns,qspi-nor-peripheral-props.yaml#