Commit f88f658f authored by CaiJian's avatar CaiJian Committed by JiangShui
Browse files

Revert "perf/smmuv3: Enable HiSilicon Erratum quirk"

driver inclusion
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/I798Y2


CVE: NA

------------------------------------------------------------------

This reverts commit fda37f5b.

Signed-off-by: default avatarCaiJian <caijian11@h-partners.com>
parent 975c4554
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+0 −3
Original line number Diff line number Diff line
@@ -1478,9 +1478,6 @@ static struct acpi_platform_list pmcg_plat_info[] __initdata = {
	/* HiSilicon Hip08 Platform */
	{"HISI  ", "HIP08   ", 0, ACPI_SIG_IORT, greater_than_or_equal,
	 "Erratum #162001800", IORT_SMMU_V3_PMCG_HISI_HIP08},
	/* HiSilicon Hip09 Platform */
	{"HISI  ", "HIP09   ", 0, ACPI_SIG_IORT, greater_than_or_equal,
	 "Erratum #162001900", IORT_SMMU_V3_PMCG_HISI_HIP09},
	{ }
};

+1 −21
Original line number Diff line number Diff line
@@ -96,7 +96,6 @@
#define SMMU_PMCG_PA_SHIFT              12

#define SMMU_PMCG_EVCNTR_RDONLY         BIT(0)
#define SMMU_PMCG_DISABLE_HARDEN        BIT(1)

static int cpuhp_state_num;

@@ -141,26 +140,10 @@ static inline void smmu_pmu_enable(struct pmu *pmu)
	writel(SMMU_PMCG_CR_ENABLE, smmu_pmu->reg_base + SMMU_PMCG_CR);
}

static inline void smmu_pmu_disable_harden(struct smmu_pmu *smmu_pmu)
{
	unsigned int idx;

	/*
	 * The global disable of PMU sometimes fail to stop the counting.
	 * Harden this by writing an invalid event type to each used counter
	 * to forcibly stop counting.
	 */
	for_each_set_bit(idx, smmu_pmu->used_counters, smmu_pmu->num_counters)
		writel(0xffff, smmu_pmu->reg_base + SMMU_PMCG_EVTYPER(idx));
}

static inline void smmu_pmu_disable(struct pmu *pmu)
{
	struct smmu_pmu *smmu_pmu = to_smmu_pmu(pmu);

	if (smmu_pmu->options & SMMU_PMCG_DISABLE_HARDEN)
		smmu_pmu_disable_harden(smmu_pmu);

	writel(0, smmu_pmu->reg_base + SMMU_PMCG_CR);
	writel(0, smmu_pmu->reg_base + SMMU_PMCG_IRQ_CTRL);
}
@@ -773,10 +756,7 @@ static void smmu_pmu_get_acpi_options(struct smmu_pmu *smmu_pmu)
	switch (model) {
	case IORT_SMMU_V3_PMCG_HISI_HIP08:
		/* HiSilicon Erratum 162001800 */
		smmu_pmu->options |= SMMU_PMCG_EVCNTR_RDONLY | SMMU_PMCG_DISABLE_HARDEN;
		break;
	case IORT_SMMU_V3_PMCG_HISI_HIP09:
		smmu_pmu->options |= SMMU_PMCG_DISABLE_HARDEN;
		smmu_pmu->options |= SMMU_PMCG_EVCNTR_RDONLY;
		break;
	}

+0 −1
Original line number Diff line number Diff line
@@ -21,7 +21,6 @@
 */
#define IORT_SMMU_V3_PMCG_GENERIC        0x00000000 /* Generic SMMUv3 PMCG */
#define IORT_SMMU_V3_PMCG_HISI_HIP08     0x00000001 /* HiSilicon HIP08 PMCG */
#define IORT_SMMU_V3_PMCG_HISI_HIP09     0x00000002 /* HiSilicon HIP09 PMCG */

int iort_register_domain_token(int trans_id, phys_addr_t base,
			       struct fwnode_handle *fw_node);