Commit f882a1e2 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'mtk-clk-for-6.1' of... 

Merge tag 'mtk-clk-for-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/wens/linux into clk-mtk

Pull MediaTek clk driver updates from Chen-Yu Tsai:

A lot of clean up work, as well as new drivers and new functions

 - New clock drivers for MediaTek Helio X10 MT6795
 - Add missing DPI1_HDMI clock in MT8195 VDOSYS1
 - Clock driver changes to support GPU DVFS on MT8183, MT8192, MT8195
   - Fix GPU clock topology on MT8195
   - Propogate rate changes from GPU clock gate up the tree
   - Clock mux notifiers for GPU-related PLLs
 - Conversion of more "simple" drivers to mtk_clk_simple_probe()
 - Hook up mtk_clk_simple_remove() for "simple" MT8192 clock drivers
 - Fixes to previous |struct clk| to |struct clk_hw| conversion
 - Shrink MT8192 clock driver by deduplicating clock parent lists

* tag 'mtk-clk-for-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/wens/linux: (31 commits)
  clk: mediatek: mt8192: deduplicate parent clock lists
  clk: mediatek: Migrate remaining clk_unregister_*() to clk_hw_unregister_*()
  clk: mediatek: fix unregister function in mtk_clk_register_dividers cleanup
  clk: mediatek: clk-mt8192: Add clock mux notifier for mfg_pll_sel
  clk: mediatek: clk-mt8192-mfg: Propagate rate changes to parent
  clk: mediatek: clk-mt8195-topckgen: Drop univplls from mfg mux parents
  clk: mediatek: clk-mt8195-topckgen: Add GPU clock mux notifier
  clk: mediatek: clk-mt8195-topckgen: Register mfg_ck_fast_ref as generic mux
  clk: mediatek: clk-mt8195-mfg: Reparent mfg_bg3d and propagate rate changes
  clk: mediatek: mt8183: Add clk mux notifier for MFG mux
  clk: mediatek: mux: add clk notifier functions
  clk: mediatek: mt8183: mfgcfg: Propagate rate changes to parent
  clk: mediatek: Use mtk_clk_register_gates_with_dev in simple probe
  clk: mediatek: gate: Export mtk_clk_register_gates_with_dev
  clk: mediatek: add VDOSYS1 clock
  dt-bindings: clk: mediatek: Add MT8195 DPI clocks
  clk: mediatek: mt8192: add mtk_clk_simple_remove
  clk: mediatek: mt8183: use mtk_clk_simple_probe to simplify driver
  clk: mediatek: mt6797: use mtk_clk_simple_probe to simplify driver
  clk: mediatek: mt6779: use mtk_clk_simple_probe to simplify driver
  ...
parents 3cc53c57 99f3a5e8

Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml

+2 −0
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ properties: 
              - mediatek,mt2701-infracfg

              - mediatek,mt2712-infracfg

              - mediatek,mt6765-infracfg

              - mediatek,mt6795-infracfg

              - mediatek,mt6779-infracfg_ao

              - mediatek,mt6797-infracfg

              - mediatek,mt7622-infracfg
@@ -60,6 +61,7 @@ if: 
        enum:

          - mediatek,mt2701-infracfg

          - mediatek,mt2712-infracfg

          - mediatek,mt6795-infracfg

          - mediatek,mt7622-infracfg

          - mediatek,mt7986-infracfg

          - mediatek,mt8135-infracfg

Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml

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Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ properties: 
              - mediatek,mt2712-mmsys

              - mediatek,mt6765-mmsys

              - mediatek,mt6779-mmsys

              - mediatek,mt6795-mmsys

              - mediatek,mt6797-mmsys

              - mediatek,mt8167-mmsys

              - mediatek,mt8173-mmsys

Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml

+1 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ properties: 
              - mediatek,mt2701-pericfg

              - mediatek,mt2712-pericfg

              - mediatek,mt6765-pericfg

              - mediatek,mt6795-pericfg

              - mediatek,mt7622-pericfg

              - mediatek,mt7629-pericfg

              - mediatek,mt8135-pericfg

Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml

+1 −0
Original line number Diff line number Diff line
@@ -34,6 +34,7 @@ properties: 
              - mediatek,mt2712-apmixedsys

              - mediatek,mt6765-apmixedsys

              - mediatek,mt6779-apmixedsys

              - mediatek,mt6795-apmixedsys

              - mediatek,mt7629-apmixedsys

              - mediatek,mt8167-apmixedsys

              - mediatek,mt8183-apmixedsys

Documentation/devicetree/bindings/clock/mediatek,mt6795-clock.yaml

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+66 −0
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/mediatek,mt6795-clock.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: MediaTek Functional Clock Controller for MT6795



maintainers:

  - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

  - Chun-Jie Chen <chun-jie.chen@mediatek.com>



description: |

  The clock architecture in MediaTek like below

  PLLs -->

          dividers -->

                      muxes

                           -->

                              clock gate



  The devices provide clock gate control in different IP blocks.



properties:

  compatible:

    enum:

      - mediatek,mt6795-mfgcfg

      - mediatek,mt6795-vdecsys

      - mediatek,mt6795-vencsys



  reg:

    maxItems: 1



  '#clock-cells':

    const: 1



required:

  - compatible

  - reg

  - '#clock-cells'



additionalProperties: false



examples:

  - |

    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        mfgcfg: clock-controller@13000000 {

            compatible = "mediatek,mt6795-mfgcfg";

            reg = <0 0x13000000 0 0x1000>;

            #clock-cells = <1>;

        };



        vdecsys: clock-controller@16000000 {

            compatible = "mediatek,mt6795-vdecsys";

            reg = <0 0x16000000 0 0x1000>;

            #clock-cells = <1>;

        };



        vencsys: clock-controller@18000000 {

            compatible = "mediatek,mt6795-vencsys";

            reg = <0 0x18000000 0 0x1000>;

            #clock-cells = <1>;

        };

    };