Commit f872f736 authored by Sumeet Pawnikar's avatar Sumeet Pawnikar Committed by Rafael J. Wysocki
Browse files

thermal: int340x: Fix VCoRefLow MMIO bit offset for TGL 



The VCoRefLow CPU FIVR register definition for Tiger Lake is incorrect.

Current implementation reads it from MMIO offset 0x5A18 and bit
offset [12:14], but the actual correct register definition is from
bit offset [11:13].

Update to fix the bit offset.

Fixes: 473be511 ("thermal: int340x: processor_thermal: Add RFIM driver")
Signed-off-by: default avatarSumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Cc: 5.14+ <stable@vger.kernel.org> # 5.14+
[ rjw: New subject, changelog edits ]
Signed-off-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
parent 0fcfb00b

drivers/thermal/intel/int340x_thermal/processor_thermal_rfim.c

+1 −1
Original line number Diff line number Diff line
@@ -29,7 +29,7 @@ static const char * const fivr_strings[] = { 
};



static const struct mmio_reg tgl_fivr_mmio_regs[] = {

	{ 0, 0x5A18, 3, 0x7, 12}, /* vco_ref_code_lo */

	{ 0, 0x5A18, 3, 0x7, 11}, /* vco_ref_code_lo */

	{ 0, 0x5A18, 8, 0xFF, 16}, /* vco_ref_code_hi */

	{ 0, 0x5A08, 8, 0xFF, 0}, /* spread_spectrum_pct */

	{ 0, 0x5A08, 1, 0x1, 8}, /* spread_spectrum_clk_enable */