Commit f84a8161 authored by Tony Cheng's avatar Tony Cheng Committed by Alex Deucher
Browse files

drm/amd/display: mode change without breaking unaffected streams



- include clock constraint logic in validate
- in dc_commit_streams, include surfaces of unaffected streams

Signed-off-by: default avatarYongqiang Sun <yongqiang.sun@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 858058da
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+9 −2
Original line number Diff line number Diff line
@@ -1007,7 +1007,7 @@ bool dc_commit_streams(
	struct dc_bios *dcb = core_dc->ctx->dc_bios;
	enum dc_status result = DC_ERROR_UNEXPECTED;
	struct validate_context *context;
	struct dc_validation_set set[MAX_STREAMS];
	struct dc_validation_set set[MAX_STREAMS] = { 0 };
	int i, j, k;

	if (false == streams_changed(core_dc, streams, stream_count))
@@ -1018,13 +1018,20 @@ bool dc_commit_streams(

	for (i = 0; i < stream_count; i++) {
		const struct dc_stream *stream = streams[i];
		const struct dc_stream_status *status = dc_stream_get_status(stream);
		int j;

		dc_stream_log(stream,
				core_dc->ctx->logger,
				LOG_DC);

		set[i].stream = stream;
		set[i].surface_count = 0;

		if (status) {
			set[i].surface_count = status->surface_count;
			for (j = 0; j < status->surface_count; j++)
				set[i].surfaces[j] = status->surfaces[j];
		}

	}

+1 −1
Original line number Diff line number Diff line
@@ -585,7 +585,7 @@ enum dc_status resource_build_scaling_params_for_context(
			if (!resource_build_scaling_params(
				&context->res_ctx.pipe_ctx[i].surface->public,
				&context->res_ctx.pipe_ctx[i]))
				return DC_FAIL_BANDWIDTH_VALIDATE;
				return DC_FAIL_SCALING;
	}

	return DC_OK;
+2 −0
Original line number Diff line number Diff line
@@ -40,6 +40,8 @@ enum dc_status {
	DC_EXCEED_DONGLE_MAX_CLK,
	DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED,
	DC_FAIL_BANDWIDTH_VALIDATE, /* BW and Watermark validation */
	DC_FAIL_SCALING,
	DC_FAIL_CLK_CONSTRAINT,

	DC_ERROR_UNEXPECTED = -1
};