Commit f844eb48 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/kms/nv50-: use NVIDIA's headers for wndw image_set() 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
Reviewed-by: default avatarLyude Paul <lyude@redhat.com>
parent 66f7b7bd

drivers/gpu/drm/nouveau/dispnv50/base507c.c

+35 −17
Original line number Diff line number Diff line
@@ -70,25 +70,43 @@ base507c_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) 
	if ((ret = PUSH_WAIT(push, 13)))

		return ret;



	PUSH_NVSQ(push, NV507C, 0x0084, asyw->image.mode << 8 |

					asyw->image.interval << 4);

	PUSH_NVSQ(push, NV507C, 0x00c0, asyw->image.handle[0]);

	if (asyw->image.format == 0xca) {

		PUSH_NVSQ(push, NV507C, 0x0110, 1,

					0x0114, 0x6400);

	PUSH_MTHD(push, NV507C, SET_PRESENT_CONTROL,

		  NVVAL(NV507C, SET_PRESENT_CONTROL, BEGIN_MODE, asyw->image.mode) |

		  NVVAL(NV507C, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, asyw->image.interval));



	PUSH_MTHD(push, NV507C, SET_CONTEXT_DMA_ISO, asyw->image.handle[0]);



	if (asyw->image.format == NV507C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16) {

		PUSH_MTHD(push, NV507C, SET_PROCESSING,

			  NVDEF(NV507C, SET_PROCESSING, USE_GAIN_OFS, ENABLE),



					SET_CONVERSION,

			  NVVAL(NV507C, SET_CONVERSION, GAIN, 0) |

			  NVVAL(NV507C, SET_CONVERSION, OFS, 0x64));

	} else {

		PUSH_NVSQ(push, NV507C, 0x0110, 0,

					0x0114, 0);

		PUSH_MTHD(push, NV507C, SET_PROCESSING,

			  NVDEF(NV507C, SET_PROCESSING, USE_GAIN_OFS, DISABLE));

	}

	PUSH_NVSQ(push, NV507C, 0x0800, asyw->image.offset[0] >> 8,

				0x0804, 0x00000000,

				0x0808, asyw->image.h << 16 | asyw->image.w,

				0x080c, asyw->image.layout << 20 |

				       (asyw->image.pitch[0] >> 8) << 8 |

				        asyw->image.blocks[0] << 8 |

					asyw->image.blockh,

				0x0810, asyw->image.kind << 16 |

					asyw->image.format << 8);



	PUSH_MTHD(push, NV507C, SURFACE_SET_OFFSET(0, 0), asyw->image.offset[0] >> 8);



	PUSH_MTHD(push, NV507C, SURFACE_SET_SIZE(0),

		  NVVAL(NV507C, SURFACE_SET_SIZE, WIDTH, asyw->image.w) |

		  NVVAL(NV507C, SURFACE_SET_SIZE, HEIGHT, asyw->image.h),



				SURFACE_SET_STORAGE(0),

		  NVVAL(NV507C, SURFACE_SET_STORAGE, MEMORY_LAYOUT, asyw->image.layout) |

		  NVVAL(NV507C, SURFACE_SET_STORAGE, PITCH, asyw->image.pitch[0] >> 8) |

		  NVVAL(NV507C, SURFACE_SET_STORAGE, PITCH, asyw->image.blocks[0]) |

		  NVVAL(NV507C, SURFACE_SET_STORAGE, BLOCK_HEIGHT, asyw->image.blockh),



				SURFACE_SET_PARAMS(0),

		  NVVAL(NV507C, SURFACE_SET_PARAMS, FORMAT, asyw->image.format) |

		  NVDEF(NV507C, SURFACE_SET_PARAMS, SUPER_SAMPLE, X1_AA) |

		  NVDEF(NV507C, SURFACE_SET_PARAMS, GAMMA, LINEAR) |

		  NVDEF(NV507C, SURFACE_SET_PARAMS, LAYOUT, FRM) |

		  NVVAL(NV507C, SURFACE_SET_PARAMS, KIND, asyw->image.kind) |

		  NVDEF(NV507C, SURFACE_SET_PARAMS, PART_STRIDE, PARTSTRIDE_256));

	return 0;

}

drivers/gpu/drm/nouveau/dispnv50/base827c.c

+36 −16
Original line number Diff line number Diff line
@@ -23,6 +23,8 @@ 


#include <nvif/push507c.h>



#include <nvhw/class/cl827c.h>



static int

base827c_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)

{
@@ -32,24 +34,42 @@ base827c_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) 
	if ((ret = PUSH_WAIT(push, 13)))

		return ret;



	PUSH_NVSQ(push, NV827C, 0x0084, asyw->image.mode << 8 |

					asyw->image.interval << 4);

	PUSH_NVSQ(push, NV827C, 0x00c0, asyw->image.handle[0]);

	if (asyw->image.format == 0xca) {

		PUSH_NVSQ(push, NV827C, 0x0110, 1,

					0x0114, 0x6400);

	PUSH_MTHD(push, NV827C, SET_PRESENT_CONTROL,

		  NVVAL(NV827C, SET_PRESENT_CONTROL, BEGIN_MODE, asyw->image.mode) |

		  NVVAL(NV827C, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, asyw->image.interval));



	PUSH_MTHD(push, NV827C, SET_CONTEXT_DMAS_ISO(0), asyw->image.handle, 1);



	if (asyw->image.format == NV827C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16) {

		PUSH_MTHD(push, NV827C, SET_PROCESSING,

			  NVDEF(NV827C, SET_PROCESSING, USE_GAIN_OFS, ENABLE),



					SET_CONVERSION,

			  NVVAL(NV827C, SET_CONVERSION, GAIN, 0) |

			  NVVAL(NV827C, SET_CONVERSION, OFS, 0x64));

	} else {

		PUSH_NVSQ(push, NV827C, 0x0110, 0,

					0x0114, 0);

		PUSH_MTHD(push, NV827C, SET_PROCESSING,

			  NVDEF(NV827C, SET_PROCESSING, USE_GAIN_OFS, DISABLE));

	}

	PUSH_NVSQ(push, NV827C, 0x0800, asyw->image.offset[0] >> 8,

				0x0804, 0x00000000,

				0x0808, asyw->image.h << 16 | asyw->image.w,

				0x080c, asyw->image.layout << 20 |

				       (asyw->image.pitch[0] >> 8) << 8 |

				        asyw->image.blocks[0] << 8 |

					asyw->image.blockh,

				0x0810, asyw->image.format << 8);



	PUSH_MTHD(push, NV827C, SURFACE_SET_OFFSET(0, 0), asyw->image.offset[0] >> 8,

				SURFACE_SET_OFFSET(0, 1), 0x00000000,



				SURFACE_SET_SIZE(0),

		  NVVAL(NV827C, SURFACE_SET_SIZE, WIDTH, asyw->image.w) |

		  NVVAL(NV827C, SURFACE_SET_SIZE, HEIGHT, asyw->image.h),



				SURFACE_SET_STORAGE(0),

		  NVVAL(NV827C, SURFACE_SET_STORAGE, BLOCK_HEIGHT, asyw->image.blockh) |

		  NVVAL(NV827C, SURFACE_SET_STORAGE, PITCH, asyw->image.pitch[0] >> 8) |

		  NVVAL(NV827C, SURFACE_SET_STORAGE, PITCH, asyw->image.blocks[0]) |

		  NVVAL(NV827C, SURFACE_SET_STORAGE, MEMORY_LAYOUT, asyw->image.layout),



				SURFACE_SET_PARAMS(0),

		  NVVAL(NV827C, SURFACE_SET_PARAMS, FORMAT, asyw->image.format) |

		  NVDEF(NV827C, SURFACE_SET_PARAMS, SUPER_SAMPLE, X1_AA) |

		  NVDEF(NV827C, SURFACE_SET_PARAMS, GAMMA, LINEAR) |

		  NVDEF(NV827C, SURFACE_SET_PARAMS, LAYOUT, FRM));

	return 0;

}

drivers/gpu/drm/nouveau/dispnv50/base907c.c

+25 −11
Original line number Diff line number Diff line
@@ -34,17 +34,31 @@ base907c_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) 
	if ((ret = PUSH_WAIT(push, 10)))

		return ret;



	PUSH_NVSQ(push, NV907C, 0x0084, asyw->image.mode << 8 |

					asyw->image.interval << 4);

	PUSH_NVSQ(push, NV907C, 0x00c0, asyw->image.handle[0]);

	PUSH_NVSQ(push, NV907C, 0x0400, asyw->image.offset[0] >> 8,

				0x0404, 0x00000000,

				0x0408, asyw->image.h << 16 | asyw->image.w,

				0x040c, asyw->image.layout << 24 |

				       (asyw->image.pitch[0] >> 8) << 8 |

				        asyw->image.blocks[0] << 8 |

					asyw->image.blockh,

				0x0410, asyw->image.format << 8);

	PUSH_MTHD(push, NV907C, SET_PRESENT_CONTROL,

		  NVVAL(NV907C, SET_PRESENT_CONTROL, BEGIN_MODE, asyw->image.mode) |

		  NVDEF(NV907C, SET_PRESENT_CONTROL, TIMESTAMP_MODE, DISABLE) |

		  NVVAL(NV907C, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, asyw->image.interval));



	PUSH_MTHD(push, NV907C, SET_CONTEXT_DMAS_ISO(0), asyw->image.handle, 1);



	PUSH_MTHD(push, NV907C, SURFACE_SET_OFFSET(0, 0), asyw->image.offset[0] >> 8,

				SURFACE_SET_OFFSET(0, 1), 0x00000000,



				SURFACE_SET_SIZE(0),

		  NVVAL(NV907C, SURFACE_SET_SIZE, WIDTH, asyw->image.w) |

		  NVVAL(NV907C, SURFACE_SET_SIZE, HEIGHT, asyw->image.h),



				SURFACE_SET_STORAGE(0),

		  NVVAL(NV907C, SURFACE_SET_STORAGE, BLOCK_HEIGHT, asyw->image.blockh) |

		  NVVAL(NV907C, SURFACE_SET_STORAGE, PITCH, asyw->image.pitch[0] >> 8) |

		  NVVAL(NV907C, SURFACE_SET_STORAGE, PITCH, asyw->image.blocks[0]) |

		  NVVAL(NV907C, SURFACE_SET_STORAGE, MEMORY_LAYOUT, asyw->image.layout),



				SURFACE_SET_PARAMS(0),

		  NVVAL(NV907C, SURFACE_SET_PARAMS, FORMAT, asyw->image.format) |

		  NVDEF(NV907C, SURFACE_SET_PARAMS, SUPER_SAMPLE, X1_AA) |

		  NVDEF(NV907C, SURFACE_SET_PARAMS, GAMMA, LINEAR) |

		  NVDEF(NV907C, SURFACE_SET_PARAMS, LAYOUT, FRM));

	return 0;

}

drivers/gpu/drm/nouveau/dispnv50/ovly507e.c

+28 −12
Original line number Diff line number Diff line
@@ -30,6 +30,8 @@ 
#include <nvif/event.h>

#include <nvif/push507c.h>



#include <nvhw/class/cl507e.h>



int

ovly507e_scale_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)

{
@@ -54,18 +56,32 @@ ovly507e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) 
	if ((ret = PUSH_WAIT(push, 12)))

		return ret;



	PUSH_NVSQ(push, NV507E, 0x0084, asyw->image.interval << 4);

	PUSH_NVSQ(push, NV507E, 0x00c0, asyw->image.handle[0]);

	PUSH_NVSQ(push, NV507E, 0x0100, 0x00000002);

	PUSH_NVSQ(push, NV507E, 0x0800, asyw->image.offset[0] >> 8);

	PUSH_NVSQ(push, NV507E, 0x0808, asyw->image.h << 16 | asyw->image.w,

				0x080c, asyw->image.layout << 20 |

				       (asyw->image.pitch[0] >> 8) << 8 |

					asyw->image.blocks[0] << 8 |

					asyw->image.blockh,

				0x0810, asyw->image.kind << 16 |

					asyw->image.format << 8 |

					asyw->image.colorspace);

	PUSH_MTHD(push, NV507E, SET_PRESENT_CONTROL,

		  NVDEF(NV507E, SET_PRESENT_CONTROL, BEGIN_MODE, ASAP) |

		  NVVAL(NV507E, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, asyw->image.interval));



	PUSH_MTHD(push, NV507E, SET_CONTEXT_DMA_ISO, asyw->image.handle[0]);



	PUSH_MTHD(push, NV507E, SET_COMPOSITION_CONTROL,

		  NVDEF(NV507E, SET_COMPOSITION_CONTROL, MODE, OPAQUE_SUSPEND_BASE));



	PUSH_MTHD(push, NV507E, SURFACE_SET_OFFSET, asyw->image.offset[0] >> 8);



	PUSH_MTHD(push, NV507E, SURFACE_SET_SIZE,

		  NVVAL(NV507E, SURFACE_SET_SIZE, WIDTH, asyw->image.w) |

		  NVVAL(NV507E, SURFACE_SET_SIZE, HEIGHT, asyw->image.h),



				SURFACE_SET_STORAGE,

		  NVVAL(NV507E, SURFACE_SET_STORAGE, BLOCK_HEIGHT, asyw->image.blockh) |

		  NVVAL(NV507E, SURFACE_SET_STORAGE, PITCH, (asyw->image.pitch[0] >> 8)) |

		  NVVAL(NV507E, SURFACE_SET_STORAGE, PITCH, asyw->image.blocks[0]) |

		  NVVAL(NV507E, SURFACE_SET_STORAGE, MEMORY_LAYOUT, asyw->image.layout),



				SURFACE_SET_PARAMS,

		  NVVAL(NV507E, SURFACE_SET_PARAMS, FORMAT, asyw->image.format) |

		  NVVAL(NV507E, SURFACE_SET_PARAMS, COLOR_SPACE, asyw->image.colorspace) |

		  NVVAL(NV507E, SURFACE_SET_PARAMS, KIND, asyw->image.kind) |

		  NVDEF(NV507E, SURFACE_SET_PARAMS, PART_STRIDE, PARTSTRIDE_256));

	return 0;

}

drivers/gpu/drm/nouveau/dispnv50/ovly827e.c

+24 −11
Original line number Diff line number Diff line
@@ -38,17 +38,30 @@ ovly827e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) 
	if ((ret = PUSH_WAIT(push, 12)))

		return ret;



	PUSH_NVSQ(push, NV827E, 0x0084, asyw->image.interval << 4);

	PUSH_NVSQ(push, NV827E, 0x00c0, asyw->image.handle[0]);

	PUSH_NVSQ(push, NV827E, 0x0100, 0x00000002);

	PUSH_NVSQ(push, NV827E, 0x0800, asyw->image.offset[0] >> 8);

	PUSH_NVSQ(push, NV827E, 0x0808, asyw->image.h << 16 | asyw->image.w,

				0x080c, asyw->image.layout << 20 |

				       (asyw->image.pitch[0] >> 8) << 8 |

					asyw->image.blocks[0] << 8 |

					asyw->image.blockh,

				0x0810, asyw->image.format << 8 |

					asyw->image.colorspace);

	PUSH_MTHD(push, NV827E, SET_PRESENT_CONTROL,

		  NVDEF(NV827E, SET_PRESENT_CONTROL, BEGIN_MODE, ASAP) |

		  NVVAL(NV827E, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, asyw->image.interval));



	PUSH_MTHD(push, NV827E, SET_CONTEXT_DMA_ISO, asyw->image.handle[0]);



	PUSH_MTHD(push, NV827E, SET_COMPOSITION_CONTROL,

		  NVDEF(NV827E, SET_COMPOSITION_CONTROL, MODE, OPAQUE_SUSPEND_BASE));



	PUSH_MTHD(push, NV827E, SURFACE_SET_OFFSET, asyw->image.offset[0] >> 8);



	PUSH_MTHD(push, NV827E, SURFACE_SET_SIZE,

		  NVVAL(NV827E, SURFACE_SET_SIZE, WIDTH, asyw->image.w) |

		  NVVAL(NV827E, SURFACE_SET_SIZE, HEIGHT, asyw->image.h),



				SURFACE_SET_STORAGE,

		  NVVAL(NV827E, SURFACE_SET_STORAGE, BLOCK_HEIGHT, asyw->image.blockh) |

		  NVVAL(NV827E, SURFACE_SET_STORAGE, PITCH, (asyw->image.pitch[0] >> 8)) |

		  NVVAL(NV827E, SURFACE_SET_STORAGE, PITCH, asyw->image.blocks[0]) |

		  NVVAL(NV827E, SURFACE_SET_STORAGE, MEMORY_LAYOUT, asyw->image.layout),



				SURFACE_SET_PARAMS,

		  NVVAL(NV827E, SURFACE_SET_PARAMS, FORMAT, asyw->image.format) |

		  NVVAL(NV827E, SURFACE_SET_PARAMS, COLOR_SPACE, asyw->image.colorspace));

	return 0;

}