Commit f83974a4 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915: split out intel_pm_types.h 



This is far from ideal, but it reduces the i915_drv.h dependency from
intel_display_types.h. Maybe in the future we'll need a better split.

Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/c6c60d9a8f6dcd1fa2f4b187000c5bb6843a1371.1638366969.git.jani.nikula@intel.com
parent 1538f65f

drivers/gpu/drm/i915/display/intel_display_types.h

+1 −0
Original line number Diff line number Diff line
@@ -47,6 +47,7 @@ 
#include <media/cec-notifier.h>



#include "i915_drv.h"

#include "intel_pm_types.h"



struct drm_printer;

struct __intel_global_objs_state;

drivers/gpu/drm/i915/i915_drv.h

+1 −63
Original line number Diff line number Diff line
@@ -89,6 +89,7 @@ 
#include "intel_device_info.h"

#include "intel_memory_region.h"

#include "intel_pch.h"

#include "intel_pm_types.h"

#include "intel_runtime_pm.h"

#include "intel_step.h"

#include "intel_uncore.h"
@@ -732,69 +733,6 @@ struct intel_vbt_data { 
	struct sdvo_device_mapping sdvo_mappings[2];

};



enum intel_ddb_partitioning {

	INTEL_DDB_PART_1_2,

	INTEL_DDB_PART_5_6, /* IVB+ */

};



struct ilk_wm_values {

	u32 wm_pipe[3];

	u32 wm_lp[3];

	u32 wm_lp_spr[3];

	bool enable_fbc_wm;

	enum intel_ddb_partitioning partitioning;

};



struct g4x_pipe_wm {

	u16 plane[I915_MAX_PLANES];

	u16 fbc;

};



struct g4x_sr_wm {

	u16 plane;

	u16 cursor;

	u16 fbc;

};



struct vlv_wm_ddl_values {

	u8 plane[I915_MAX_PLANES];

};



struct vlv_wm_values {

	struct g4x_pipe_wm pipe[3];

	struct g4x_sr_wm sr;

	struct vlv_wm_ddl_values ddl[3];

	u8 level;

	bool cxsr;

};



struct g4x_wm_values {

	struct g4x_pipe_wm pipe[2];

	struct g4x_sr_wm sr;

	struct g4x_sr_wm hpll;

	bool cxsr;

	bool hpll_en;

	bool fbc_en;

};



struct skl_ddb_entry {

	u16 start, end;	/* in number of blocks, 'end' is exclusive */

};



static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)

{

	return entry->end - entry->start;

}



static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,

				       const struct skl_ddb_entry *e2)

{

	if (e1->start == e2->start && e1->end == e2->end)

		return true;



	return false;

}



struct i915_frontbuffer_tracking {

	spinlock_t lock;

drivers/gpu/drm/i915/intel_pm_types.h

0 → 100644
+76 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: MIT */

/*

 * Copyright © 2021 Intel Corporation

 */



#ifndef __INTEL_PM_TYPES_H__

#define __INTEL_PM_TYPES_H__



#include <linux/types.h>



#include "display/intel_display.h"



enum intel_ddb_partitioning {

	INTEL_DDB_PART_1_2,

	INTEL_DDB_PART_5_6, /* IVB+ */

};



struct ilk_wm_values {

	u32 wm_pipe[3];

	u32 wm_lp[3];

	u32 wm_lp_spr[3];

	bool enable_fbc_wm;

	enum intel_ddb_partitioning partitioning;

};



struct g4x_pipe_wm {

	u16 plane[I915_MAX_PLANES];

	u16 fbc;

};



struct g4x_sr_wm {

	u16 plane;

	u16 cursor;

	u16 fbc;

};



struct vlv_wm_ddl_values {

	u8 plane[I915_MAX_PLANES];

};



struct vlv_wm_values {

	struct g4x_pipe_wm pipe[3];

	struct g4x_sr_wm sr;

	struct vlv_wm_ddl_values ddl[3];

	u8 level;

	bool cxsr;

};



struct g4x_wm_values {

	struct g4x_pipe_wm pipe[2];

	struct g4x_sr_wm sr;

	struct g4x_sr_wm hpll;

	bool cxsr;

	bool hpll_en;

	bool fbc_en;

};



struct skl_ddb_entry {

	u16 start, end;	/* in number of blocks, 'end' is exclusive */

};



static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)

{

	return entry->end - entry->start;

}



static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,

				       const struct skl_ddb_entry *e2)

{

	if (e1->start == e2->start && e1->end == e2->end)

		return true;



	return false;

}



#endif /* __INTEL_PM_TYPES_H__ */