Commit f831f93a authored by Paul Cercueil's avatar Paul Cercueil Committed by Linus Walleij
Browse files

pinctrl: ingenic: Factorize irq_set_type function 



Simplify the code of the driver's irq_set_type() function by doing some
factorization. The behaviour is unchanged.

Signed-off-by: default avatarPaul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20200106232711.559727-5-paul@crapouillou.net


Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 5ffdbb7e

drivers/pinctrl/pinctrl-ingenic.c

+24 −40
Original line number Diff line number Diff line
@@ -1676,57 +1676,41 @@ static void irq_set_type(struct ingenic_gpio_chip *jzgc, 
		u8 offset, unsigned int type)

{

	u8 reg1, reg2;



	if (jzgc->jzpc->info->version >= ID_JZ4760) {

		reg1 = JZ4760_GPIO_PAT1;

		reg2 = JZ4760_GPIO_PAT0;

	} else {

		reg1 = JZ4740_GPIO_TRIG;

		reg2 = JZ4740_GPIO_DIR;

	}

	bool val1, val2;



	switch (type) {

	case IRQ_TYPE_EDGE_RISING:

		if (jzgc->jzpc->info->version >= ID_X1000) {

			ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, true);

			ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, true);

			ingenic_gpio_shadow_set_bit_load(jzgc);

		} else {

			ingenic_gpio_set_bit(jzgc, reg2, offset, true);

			ingenic_gpio_set_bit(jzgc, reg1, offset, true);

		}

		val1 = val2 = true;

		break;

	case IRQ_TYPE_EDGE_FALLING:

		if (jzgc->jzpc->info->version >= ID_X1000) {

			ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, false);

			ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, true);

			ingenic_gpio_shadow_set_bit_load(jzgc);

		} else {

			ingenic_gpio_set_bit(jzgc, reg2, offset, false);

			ingenic_gpio_set_bit(jzgc, reg1, offset, true);

		}

		val1 = false;

		val2 = true;

		break;

	case IRQ_TYPE_LEVEL_HIGH:

		if (jzgc->jzpc->info->version >= ID_X1000) {

			ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, true);

			ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, false);

			ingenic_gpio_shadow_set_bit_load(jzgc);

		} else {

			ingenic_gpio_set_bit(jzgc, reg2, offset, true);

			ingenic_gpio_set_bit(jzgc, reg1, offset, false);

		}

		val1 = true;

		val2 = false;

		break;

	case IRQ_TYPE_LEVEL_LOW:

	default:

		val1 = val2 = false;

		break;

	}



	if (jzgc->jzpc->info->version >= ID_JZ4760) {

		reg1 = JZ4760_GPIO_PAT1;

		reg2 = JZ4760_GPIO_PAT0;

	} else {

		reg1 = JZ4740_GPIO_TRIG;

		reg2 = JZ4740_GPIO_DIR;

	}



	if (jzgc->jzpc->info->version >= ID_X1000) {

			ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, false);

			ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, false);

		ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1);

		ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2);

		ingenic_gpio_shadow_set_bit_load(jzgc);

	} else {

			ingenic_gpio_set_bit(jzgc, reg2, offset, false);

			ingenic_gpio_set_bit(jzgc, reg1, offset, false);

		}

		break;

		ingenic_gpio_set_bit(jzgc, reg2, offset, val1);

		ingenic_gpio_set_bit(jzgc, reg1, offset, val2);

	}

}