Commit f828b65a authored by Wei Tian's avatar Wei Tian Committed by Tian Wei
Browse files

hda: add phytium hda driver 

phytium inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I7VDG1


CVE: NA

---------------------------

add phytium hda driver

Signed-off-by: default avatarWei Tian <tianwei@phytium.com.cn>
Signed-off-by: default avatarChen Baozi <chenbaozi@phytium.com.cn>
parent 125e2091

include/sound/hdaudio.h

+1 −0
Original line number Diff line number Diff line
@@ -354,6 +354,7 @@ struct hdac_bus { 
	bool align_bdle_4k:1;		/* BDLE align 4K boundary */

	bool reverse_assign:1;		/* assign devices in reverse order */

	bool corbrp_self_clear:1;	/* CORBRP clears itself after reset */

	bool cmd_resend;		/* command resend */



	int bdl_pos_adj;		/* BDL position adjustment */

sound/hda/hdac_controller.c

+37 −0
Original line number Diff line number Diff line
@@ -139,6 +139,9 @@ int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val) 
{

	unsigned int addr = azx_command_addr(val);

	unsigned int wp, rp;

	unsigned long timeout;

	unsigned int rirb_wp;

	int i = 0;



	spin_lock_irq(&bus->reg_lock);
@@ -165,6 +168,40 @@ int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val) 
	bus->corb.buf[wp] = cpu_to_le32(val);

	snd_hdac_chip_writew(bus, CORBWP, wp);



	if (bus->cmd_resend) {

		timeout = jiffies + msecs_to_jiffies(1000);

		udelay(80);

		rirb_wp = snd_hdac_chip_readw(bus, RIRBWP);

		while (rirb_wp == bus->rirb.wp) {

			udelay(80);

			rirb_wp = snd_hdac_chip_readw(bus, RIRBWP);

			if (rirb_wp != bus->rirb.wp)

				break;

			if (i > 5)

				break;

			if (time_after(jiffies, timeout))

				break;



			/* add command to corb */

			wp = snd_hdac_chip_readw(bus, CORBWP);

			if (wp == 0xffff) {

			/* something wrong, controller likely turned to D3 */

				spin_unlock_irq(&bus->reg_lock);

				return -EIO;

			}

			wp++;

			wp %= AZX_MAX_CORB_ENTRIES;

			rp = snd_hdac_chip_readw(bus, CORBRP);

			if (wp == rp) {

			/* oops, it's full */

				spin_unlock_irq(&bus->reg_lock);

				return -EAGAIN;

			}

			bus->corb.buf[wp] = cpu_to_le32(val);

			snd_hdac_chip_writew(bus, CORBWP, wp);

			i++;

		}

	}

	spin_unlock_irq(&bus->reg_lock);



	return 0;

sound/pci/hda/Kconfig

+15 −0
Original line number Diff line number Diff line
@@ -21,6 +21,21 @@ config SND_HDA_INTEL 
	  To compile this driver as a module, choose M here: the module

	  will be called snd-hda-intel.



config SND_HDA_PHYTIUM

	tristate "PHYTIUM HD Audio"

	depends on SOUND

	select SND_HDA

	help

	  Say Y here to support the HDA controller present in PHYTIUM

	  SoCs



	  This options enables support for the HD Audio controller

	  present in some PHYTIUM SoCs, used to communicate audio

	  to the "High Definition Audio" codec.



	  To compile this driver as a module, choose M here: the module

	  will be called snd-hda-phytium.



config SND_HDA_TEGRA

	tristate "NVIDIA Tegra HD Audio"

	depends on ARCH_TEGRA

sound/pci/hda/Makefile

+2 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

snd-hda-intel-objs := hda_intel.o

snd-hda-phytium-objs := hda_phytium.o

snd-hda-tegra-objs := hda_tegra.o



snd-hda-codec-y := hda_bind.o hda_codec.o hda_jack.o hda_auto_parser.o hda_sysfs.o
@@ -48,3 +49,4 @@ obj-$(CONFIG_SND_HDA_CODEC_HDMI) += snd-hda-codec-hdmi.o 
# when built in kernel

obj-$(CONFIG_SND_HDA_INTEL) += snd-hda-intel.o

obj-$(CONFIG_SND_HDA_TEGRA) += snd-hda-tegra.o

obj-$(CONFIG_SND_HDA_PHYTIUM) += snd-hda-phytium.o

sound/pci/hda/hda_phytium.c

0 → 100644
+1216 −0

File added.

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