Commit f80c71f7 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2022-10-28' of git://anongit.freedesktop.org/drm/drm-intel into drm-next 



- Hotplug code clean-up and organization (Jani, Gustavo)
- More VBT specific code clean-up, doc, organization,
  and improvements (Ville)
- More MTL enabling work (Matt, RK, Anusha, Jose)
- FBC related clean-ups and improvements (Ville)
- Removing unused sw_fence_await_reservation (Niranjana)
- Big chunch of display house clean-up (Ville)
- Many Watermark fixes and clean-ups (Ville)
- Fix device info for devices without display (Jani)
- Fix TC port PLLs after readout (Ville)
- DPLL ID clean-ups (Ville)
- Prep work for finishing (de)gamma readout (Ville)
- PSR fixes and improvements (Jouni, Jose)
- Reject excessive dotclocks early (Ville)
- DRRS related improvements (Ville)
- Simplify uncore register updates (Andrzej)
- Fix simulated GPU reset wrt. encoder HW readout (Imre)
- Add a ADL-P workaround (Jose)
- Fix clear mask in GEN7_MISCCPCTL update (Andrzej)
- Temporarily disable runtime_pm for discrete (Anshuman)
- Improve fbdev debugs (Nirmoy)
- Fix DP FRL link training status (Ankit)
- Other small display fixes (Ankit, Suraj)
- Allow panel fixed modes to have differing sync
  polarities (Ville)
- Clean up crtc state flag checks (Ville)
- Fix race conditions during DKL PHY accesses (Imre)
- Prep-work for cdclock squash and crawl modes (Anusha)
- ELD precompute and readout (Ville)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/Y1wd6ZJ8LdJpCfZL@intel.com
parents 2b1966c6 a6ebd538

drivers/gpu/drm/i915/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -282,6 +282,7 @@ i915-y += \ 
	display/intel_ddi.o \

	display/intel_ddi_buf_trans.o \

	display/intel_display_trace.o \

	display/intel_dkl_phy.o \

	display/intel_dp.o \

	display/intel_dp_aux.o \

	display/intel_dp_aux_backlight.o \

drivers/gpu/drm/i915/display/g4x_hdmi.c

+2 −2
Original line number Diff line number Diff line
@@ -585,7 +585,7 @@ void g4x_hdmi_init(struct drm_i915_private *dev_priv, 
	} else {

		intel_encoder->pipe_mask = ~0;

	}

	intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;

	intel_encoder->cloneable = BIT(INTEL_OUTPUT_ANALOG);

	intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);

	/*

	 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
@@ -593,7 +593,7 @@ void g4x_hdmi_init(struct drm_i915_private *dev_priv, 
	 * only one port anyway, nothing is lost by allowing it.

	 */

	if (IS_G4X(dev_priv))

		intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;

		intel_encoder->cloneable |= BIT(INTEL_OUTPUT_HDMI);



	dig_port->hdmi.hdmi_reg = hdmi_reg;

	dig_port->dp.output_reg = INVALID_MMIO_REG;

drivers/gpu/drm/i915/display/hsw_ips.c

+3 −5
Original line number Diff line number Diff line
@@ -104,8 +104,7 @@ static bool hsw_ips_need_disable(struct intel_atomic_state *state, 
	 * Disable IPS before we program the LUT.

	 */

	if (IS_HASWELL(i915) &&

	    (new_crtc_state->uapi.color_mgmt_changed ||

	     new_crtc_state->update_pipe) &&

	    intel_crtc_needs_color_update(new_crtc_state) &&

	    new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)

		return true;
@@ -146,8 +145,7 @@ static bool hsw_ips_need_enable(struct intel_atomic_state *state, 
	 * Re-enable IPS after the LUT has been programmed.

	 */

	if (IS_HASWELL(i915) &&

	    (new_crtc_state->uapi.color_mgmt_changed ||

	     new_crtc_state->update_pipe) &&

	    intel_crtc_needs_color_update(new_crtc_state) &&

	    new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)

		return true;
@@ -155,7 +153,7 @@ static bool hsw_ips_need_enable(struct intel_atomic_state *state, 
	 * We can't read out IPS on broadwell, assume the worst and

	 * forcibly enable IPS on the first fastset.

	 */

	if (new_crtc_state->update_pipe && old_crtc_state->inherited)

	if (intel_crtc_needs_fastset(new_crtc_state) && old_crtc_state->inherited)

		return true;



	return !old_crtc_state->ips_enabled;

drivers/gpu/drm/i915/display/icl_dsi.c

+5 −16
Original line number Diff line number Diff line
@@ -1974,16 +1974,8 @@ static void icl_dsi_add_properties(struct intel_connector *connector) 
{

	const struct drm_display_mode *fixed_mode =

		intel_panel_preferred_fixed_mode(connector);

	u32 allowed_scalers;



	allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) |

			   BIT(DRM_MODE_SCALE_FULLSCREEN) |

			   BIT(DRM_MODE_SCALE_CENTER);



	drm_connector_attach_scaling_mode_property(&connector->base,

						   allowed_scalers);



	connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT;

	intel_attach_scaling_mode_property(&connector->base);



	drm_connector_set_panel_orientation_with_quirk(&connector->base,

						       intel_dsi_get_panel_orientation(connector),
@@ -1993,7 +1985,6 @@ static void icl_dsi_add_properties(struct intel_connector *connector) 


void icl_dsi_init(struct drm_i915_private *dev_priv)

{

	struct drm_device *dev = &dev_priv->drm;

	struct intel_dsi *intel_dsi;

	struct intel_encoder *encoder;

	struct intel_connector *intel_connector;
@@ -2018,7 +2009,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv) 
	connector = &intel_connector->base;



	/* register DSI encoder with DRM subsystem */

	drm_encoder_init(dev, &encoder->base, &gen11_dsi_encoder_funcs,

	drm_encoder_init(&dev_priv->drm, &encoder->base, &gen11_dsi_encoder_funcs,

			 DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port));



	encoder->pre_pll_enable = gen11_dsi_pre_pll_enable;
@@ -2042,12 +2033,10 @@ void icl_dsi_init(struct drm_i915_private *dev_priv) 
	encoder->is_clock_enabled = gen11_dsi_is_clock_enabled;



	/* register DSI connector with DRM subsystem */

	drm_connector_init(dev, connector, &gen11_dsi_connector_funcs,

	drm_connector_init(&dev_priv->drm, connector, &gen11_dsi_connector_funcs,

			   DRM_MODE_CONNECTOR_DSI);

	drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs);

	connector->display_info.subpixel_order = SubPixelHorizontalRGB;

	connector->interlace_allowed = false;

	connector->doublescan_allowed = false;

	intel_connector->get_hw_state = intel_connector_get_hw_state;



	/* attach connector to encoder */
@@ -2055,9 +2044,9 @@ void icl_dsi_init(struct drm_i915_private *dev_priv) 


	intel_bios_init_panel(dev_priv, &intel_connector->panel, NULL, NULL);



	mutex_lock(&dev->mode_config.mutex);

	mutex_lock(&dev_priv->drm.mode_config.mutex);

	intel_panel_add_vbt_lfp_fixed_mode(intel_connector);

	mutex_unlock(&dev->mode_config.mutex);

	mutex_unlock(&dev_priv->drm.mode_config.mutex);



	if (!intel_panel_preferred_fixed_mode(intel_connector)) {

		drm_err(&dev_priv->drm, "DSI fixed mode info missing\n");

drivers/gpu/drm/i915/display/intel_atomic.c

+8 −0
Original line number Diff line number Diff line
@@ -252,6 +252,11 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc) 
	if (crtc_state->hw.gamma_lut)

		drm_property_blob_get(crtc_state->hw.gamma_lut);



	if (crtc_state->pre_csc_lut)

		drm_property_blob_get(crtc_state->pre_csc_lut);

	if (crtc_state->post_csc_lut)

		drm_property_blob_get(crtc_state->post_csc_lut);



	crtc_state->update_pipe = false;

	crtc_state->disable_lp_wm = false;

	crtc_state->disable_cxsr = false;
@@ -274,6 +279,9 @@ static void intel_crtc_put_color_blobs(struct intel_crtc_state *crtc_state) 
	drm_property_blob_put(crtc_state->hw.degamma_lut);

	drm_property_blob_put(crtc_state->hw.gamma_lut);

	drm_property_blob_put(crtc_state->hw.ctm);



	drm_property_blob_put(crtc_state->pre_csc_lut);

	drm_property_blob_put(crtc_state->post_csc_lut);

}



void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state)