Commit f801efb1 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/kms/nv50-: use NVIDIA's headers for core head_dither() 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
Reviewed-by: default avatarLyude Paul <lyude@redhat.com>
parent 35cefc53

drivers/gpu/drm/nouveau/dispnv50/head.c

+3 −3
Original line number Diff line number Diff line
@@ -106,9 +106,9 @@ nv50_head_atomic_check_dither(struct nv50_head_atom *armh, 
		}

	}



	asyh->dither.enable = mode;

	asyh->dither.bits = mode >> 1;

	asyh->dither.mode = mode >> 3;

	asyh->dither.enable = NVVAL_GET(mode, NV507D, HEAD_SET_DITHER_CONTROL, ENABLE);

	asyh->dither.bits = NVVAL_GET(mode, NV507D, HEAD_SET_DITHER_CONTROL, BITS);

	asyh->dither.mode = NVVAL_GET(mode, NV507D, HEAD_SET_DITHER_CONTROL, MODE);

	asyh->set.dither = true;

}

drivers/gpu/drm/nouveau/dispnv50/head507d.c

+5 −3
Original line number Diff line number Diff line
@@ -51,9 +51,11 @@ head507d_dither(struct nv50_head *head, struct nv50_head_atom *asyh) 
	if ((ret = PUSH_WAIT(push, 2)))

		return ret;



	PUSH_NVSQ(push, NV507D, 0x08a0 + (i * 0x400), asyh->dither.mode << 3 |

						      asyh->dither.bits << 1 |

						      asyh->dither.enable);

	PUSH_MTHD(push, NV507D, HEAD_SET_DITHER_CONTROL(i),

		  NVVAL(NV507D, HEAD_SET_DITHER_CONTROL, ENABLE, asyh->dither.enable) |

		  NVVAL(NV507D, HEAD_SET_DITHER_CONTROL, BITS, asyh->dither.bits) |

		  NVVAL(NV507D, HEAD_SET_DITHER_CONTROL, MODE, asyh->dither.mode) |

		  NVVAL(NV507D, HEAD_SET_DITHER_CONTROL, PHASE, 0));

	return 0;

}

drivers/gpu/drm/nouveau/dispnv50/head907d.c

+5 −3
Original line number Diff line number Diff line
@@ -78,9 +78,11 @@ head907d_dither(struct nv50_head *head, struct nv50_head_atom *asyh) 
	if ((ret = PUSH_WAIT(push, 2)))

		return ret;



	PUSH_NVSQ(push, NV907D, 0x0490 + (i * 0x300), asyh->dither.mode << 3 |

						      asyh->dither.bits << 1 |

						      asyh->dither.enable);

	PUSH_MTHD(push, NV907D, HEAD_SET_DITHER_CONTROL(i),

		  NVVAL(NV907D, HEAD_SET_DITHER_CONTROL, ENABLE, asyh->dither.enable) |

		  NVVAL(NV907D, HEAD_SET_DITHER_CONTROL, BITS, asyh->dither.bits) |

		  NVVAL(NV907D, HEAD_SET_DITHER_CONTROL, MODE, asyh->dither.mode) |

		  NVVAL(NV907D, HEAD_SET_DITHER_CONTROL, PHASE, 0));

	return 0;

}

drivers/gpu/drm/nouveau/dispnv50/head917d.c

+5 −3
Original line number Diff line number Diff line
@@ -36,9 +36,11 @@ head917d_dither(struct nv50_head *head, struct nv50_head_atom *asyh) 
	if ((ret = PUSH_WAIT(push, 2)))

		return ret;



	PUSH_NVSQ(push, NV917D, 0x04a0 + (i * 0x300), asyh->dither.mode << 3 |

						      asyh->dither.bits << 1 |

						      asyh->dither.enable);

	PUSH_MTHD(push, NV917D, HEAD_SET_DITHER_CONTROL(i),

		  NVVAL(NV917D, HEAD_SET_DITHER_CONTROL, ENABLE, asyh->dither.enable) |

		  NVVAL(NV917D, HEAD_SET_DITHER_CONTROL, BITS, asyh->dither.bits) |

		  NVVAL(NV917D, HEAD_SET_DITHER_CONTROL, MODE, asyh->dither.mode) |

		  NVVAL(NV917D, HEAD_SET_DITHER_CONTROL, PHASE, 0));

	return 0;

}

drivers/gpu/drm/nouveau/dispnv50/headc37d.c

+6 −3
Original line number Diff line number Diff line
@@ -85,9 +85,12 @@ headc37d_dither(struct nv50_head *head, struct nv50_head_atom *asyh) 
	if ((ret = PUSH_WAIT(push, 2)))

		return ret;



	PUSH_NVSQ(push, NV907D, 0x2018 + (i * 0x400), asyh->dither.mode << 8 |

						      asyh->dither.bits << 4 |

						      asyh->dither.enable);

	PUSH_MTHD(push, NVC37D, HEAD_SET_DITHER_CONTROL(i),

		  NVVAL(NVC37D, HEAD_SET_DITHER_CONTROL, ENABLE, asyh->dither.enable) |

		  NVVAL(NVC37D, HEAD_SET_DITHER_CONTROL, BITS, asyh->dither.bits) |

		  NVDEF(NVC37D, HEAD_SET_DITHER_CONTROL, OFFSET_ENABLE, DISABLE) |

		  NVVAL(NVC37D, HEAD_SET_DITHER_CONTROL, MODE, asyh->dither.mode) |

		  NVVAL(NVC37D, HEAD_SET_DITHER_CONTROL, PHASE, 0));

	return 0;

}