Commit f7fbcf46 authored by Aurabindo Pillai's avatar Aurabindo Pillai Committed by Alex Deucher
Browse files

drm/amd/display: change to runtime initialization for reg offsets for DCN32 



DC was using compile time initialization of register addresses using
SR_* macros and their variants. These have been converted to use runtime
initialization.

The REG_STRUCT macro is a definition that is added to SR_* macros.
During initialization, this must be defined before SR_* macros are
invoked, which are in turn invoked through various IP initialization macros.

Reviewed-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Acked-by: default avatarBrian Chang <Brian.Chang@amd.com>
Signed-off-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 95bbbb88

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c

+354 −296
Original line number Diff line number Diff line
@@ -131,28 +131,48 @@ enum dcn32_clk_src_array_id { 
/* DCN */

/* TODO awful hack. fixup dcn20_dwb.h */

#undef BASE_INNER

#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg

#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]



#define BASE(seg) BASE_INNER(seg)



#define SR(reg_name)\

		.reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \

		REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \

					reg ## reg_name

#define SR_ARR(reg_name, id) \

	REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name



#define SR_ARR_INIT(reg_name, id, value) \

	REG_STRUCT[id].reg_name = value



#define SRI(reg_name, block, id)\

	.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

	REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

		reg ## block ## id ## _ ## reg_name



#define SRI_ARR(reg_name, block, id)\

	REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

		reg ## block ## id ## _ ## reg_name



#define SRI_ARR_ALPHABET(reg_name, block, index, id)\

	REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

		reg ## block ## id ## _ ## reg_name



#define SRI2(reg_name, block, id)\

	.reg_name = BASE(reg ## reg_name ## _BASE_IDX) +	\

		reg ## reg_name

#define SRI2_ARR(reg_name, block, id)\

	REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) +	\

		reg ## reg_name



#define SRIR(var_name, reg_name, block, id)\

	.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

		reg ## block ## id ## _ ## reg_name



#define SRII(reg_name, block, id)\

	.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

	REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

					reg ## block ## id ## _ ## reg_name



#define SRII_ARR_2(reg_name, block, id, inst)\

	REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

		reg ## block ## id ## _ ## reg_name



#define SRII_MPC_RMU(reg_name, block, id)\
@@ -160,50 +180,47 @@ enum dcn32_clk_src_array_id { 
		reg ## block ## id ## _ ## reg_name



#define SRII_DWB(reg_name, temp_name, block, id)\

	.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \

	REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \

		reg ## block ## id ## _ ## temp_name



#define DCCG_SRII(reg_name, block, id)\

	.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

	REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

		reg ## block ## id ## _ ## reg_name



#define VUPDATE_SRII(reg_name, block, id)\

	.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

	REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

		reg ## reg_name ## _ ## block ## id



/* NBIO */

#define NBIO_BASE_INNER(seg) \

	NBIO_BASE__INST0_SEG ## seg

#define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]



#define NBIO_BASE(seg) \

	NBIO_BASE_INNER(seg)



#define NBIO_SR(reg_name)\

		.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \

	REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \

			regBIF_BX0_ ## reg_name

#define NBIO_SR_ARR(reg_name, id)\

	REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \

		regBIF_BX0_ ## reg_name



#undef CTX

#define CTX ctx

#define REG(reg_name) \

	(DCN_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)

	(ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)



static const struct bios_registers bios_regs = {

		NBIO_SR(BIOS_SCRATCH_3),

		NBIO_SR(BIOS_SCRATCH_6)

};

static struct bios_registers bios_regs;



#define clk_src_regs(index, pllid)\

[index] = {\

	CS_COMMON_REG_LIST_DCN3_0(index, pllid),\

}

#define bios_regs_init() \

		( \

		NBIO_SR(BIOS_SCRATCH_3),\

		NBIO_SR(BIOS_SCRATCH_6)\

		)



static const struct dce110_clk_src_regs clk_src_regs[] = {

	clk_src_regs(0, A),

	clk_src_regs(1, B),

	clk_src_regs(2, C),

	clk_src_regs(3, D),

	clk_src_regs(4, E)

};

#define clk_src_regs_init(index, pllid)\

	CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid)



static struct dce110_clk_src_regs clk_src_regs[5];



static const struct dce110_clk_src_shift cs_shift = {

		CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
@@ -213,17 +230,10 @@ static const struct dce110_clk_src_mask cs_mask = { 
		CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK)

};



#define abm_regs(id)\

[id] = {\

		ABM_DCN32_REG_LIST(id)\

}

#define abm_regs_init(id)\

		ABM_DCN32_REG_LIST_RI(id)



static const struct dce_abm_registers abm_regs[] = {

		abm_regs(0),

		abm_regs(1),

		abm_regs(2),

		abm_regs(3),

};

static struct dce_abm_registers abm_regs[4];



static const struct dce_abm_shift abm_shift = {

		ABM_MASK_SH_LIST_DCN32(__SHIFT)
@@ -233,18 +243,10 @@ static const struct dce_abm_mask abm_mask = { 
		ABM_MASK_SH_LIST_DCN32(_MASK)

};



#define audio_regs(id)\

[id] = {\

		AUD_COMMON_REG_LIST(id)\

}

#define audio_regs_init(id)\

		AUD_COMMON_REG_LIST_RI(id)



static const struct dce_audio_registers audio_regs[] = {

	audio_regs(0),

	audio_regs(1),

	audio_regs(2),

	audio_regs(3),

	audio_regs(4)

};

static struct dce_audio_registers audio_regs[5];



#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\

		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
@@ -259,23 +261,10 @@ static const struct dce_audio_mask audio_mask = { 
		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)

};



#define vpg_regs(id)\

[id] = {\

	VPG_DCN3_REG_LIST(id)\

}



static const struct dcn30_vpg_registers vpg_regs[] = {

	vpg_regs(0),

	vpg_regs(1),

	vpg_regs(2),

	vpg_regs(3),

	vpg_regs(4),

	vpg_regs(5),

	vpg_regs(6),

	vpg_regs(7),

	vpg_regs(8),

	vpg_regs(9),

};

#define vpg_regs_init(id)\

	VPG_DCN3_REG_LIST_RI(id)



static struct dcn30_vpg_registers vpg_regs[10];



static const struct dcn30_vpg_shift vpg_shift = {

	DCN3_VPG_MASK_SH_LIST(__SHIFT)
@@ -285,19 +274,10 @@ static const struct dcn30_vpg_mask vpg_mask = { 
	DCN3_VPG_MASK_SH_LIST(_MASK)

};



#define afmt_regs(id)\

[id] = {\

	AFMT_DCN3_REG_LIST(id)\

}

#define afmt_regs_init(id)\

	AFMT_DCN3_REG_LIST_RI(id)



static const struct dcn30_afmt_registers afmt_regs[] = {

	afmt_regs(0),

	afmt_regs(1),

	afmt_regs(2),

	afmt_regs(3),

	afmt_regs(4),

	afmt_regs(5)

};

static struct dcn30_afmt_registers afmt_regs[6];



static const struct dcn30_afmt_shift afmt_shift = {

	DCN3_AFMT_MASK_SH_LIST(__SHIFT)
@@ -307,17 +287,10 @@ static const struct dcn30_afmt_mask afmt_mask = { 
	DCN3_AFMT_MASK_SH_LIST(_MASK)

};



#define apg_regs(id)\

[id] = {\

	APG_DCN31_REG_LIST(id)\

}

#define apg_regs_init(id)\

	APG_DCN31_REG_LIST_RI(id)



static const struct dcn31_apg_registers apg_regs[] = {

	apg_regs(0),

	apg_regs(1),

	apg_regs(2),

	apg_regs(3)

};

static struct dcn31_apg_registers apg_regs[4];



static const struct dcn31_apg_shift apg_shift = {

	DCN31_APG_MASK_SH_LIST(__SHIFT)
@@ -327,18 +300,10 @@ static const struct dcn31_apg_mask apg_mask = { 
		DCN31_APG_MASK_SH_LIST(_MASK)

};



#define stream_enc_regs(id)\

[id] = {\

	SE_DCN32_REG_LIST(id)\

}

#define stream_enc_regs_init(id)\

	SE_DCN32_REG_LIST_RI(id)



static const struct dcn10_stream_enc_registers stream_enc_regs[] = {

	stream_enc_regs(0),

	stream_enc_regs(1),

	stream_enc_regs(2),

	stream_enc_regs(3),

	stream_enc_regs(4)

};

static struct dcn10_stream_enc_registers stream_enc_regs[5];



static const struct dcn10_stream_encoder_shift se_shift = {

		SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
@@ -349,46 +314,24 @@ static const struct dcn10_stream_encoder_mask se_mask = { 
};





#define aux_regs(id)\

[id] = {\

	DCN2_AUX_REG_LIST(id)\

}

#define aux_regs_init(id)\

	DCN2_AUX_REG_LIST_RI(id)



static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {

		aux_regs(0),

		aux_regs(1),

		aux_regs(2),

		aux_regs(3),

		aux_regs(4)

};

static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5];



#define hpd_regs(id)\

[id] = {\

	HPD_REG_LIST(id)\

}

#define hpd_regs_init(id)\

	HPD_REG_LIST_RI(id)



static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {

		hpd_regs(0),

		hpd_regs(1),

		hpd_regs(2),

		hpd_regs(3),

		hpd_regs(4)

};

static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5];



#define link_regs(id, phyid)\

[id] = {\

	LE_DCN31_REG_LIST(id), \

	UNIPHY_DCN2_REG_LIST(phyid), \

#define link_regs_init(id, phyid)\

	( \

	LE_DCN31_REG_LIST_RI(id), \

	UNIPHY_DCN2_REG_LIST_RI(id, phyid)\

	)

	/*DPCS_DCN31_REG_LIST(id),*/ \

}



static const struct dcn10_link_enc_registers link_enc_regs[] = {

	link_regs(0, A),

	link_regs(1, B),

	link_regs(2, C),

	link_regs(3, D),

	link_regs(4, E)

};

static struct dcn10_link_enc_registers link_enc_regs[5];



static const struct dcn10_link_enc_shift le_shift = {

	LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
@@ -401,17 +344,10 @@ static const struct dcn10_link_enc_mask le_mask = { 
	//DPCS_DCN31_MASK_SH_LIST(_MASK)

};



#define hpo_dp_stream_encoder_reg_list(id)\

[id] = {\

	DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\

}

#define hpo_dp_stream_encoder_reg_init(id)\

	DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id)



static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {

	hpo_dp_stream_encoder_reg_list(0),

	hpo_dp_stream_encoder_reg_list(1),

	hpo_dp_stream_encoder_reg_list(2),

	hpo_dp_stream_encoder_reg_list(3),

};

static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4];



static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {

	DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
@@ -422,20 +358,14 @@ static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 
};





#define hpo_dp_link_encoder_reg_list(id)\

[id] = {\

	DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\

	/*DCN3_1_RDPCSTX_REG_LIST(0),*/\

	/*DCN3_1_RDPCSTX_REG_LIST(1),*/\

	/*DCN3_1_RDPCSTX_REG_LIST(2),*/\

	/*DCN3_1_RDPCSTX_REG_LIST(3),*/\

	/*DCN3_1_RDPCSTX_REG_LIST(4)*/\

}

#define hpo_dp_link_encoder_reg_init(id)\

	DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id)

	/*DCN3_1_RDPCSTX_REG_LIST(0),*/

	/*DCN3_1_RDPCSTX_REG_LIST(1),*/

	/*DCN3_1_RDPCSTX_REG_LIST(2),*/

	/*DCN3_1_RDPCSTX_REG_LIST(3),*/



static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {

	hpo_dp_link_encoder_reg_list(0),

	hpo_dp_link_encoder_reg_list(1),

};

static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2];



static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {

	DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
@@ -445,17 +375,10 @@ static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 
	DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)

};



#define dpp_regs(id)\

[id] = {\

	DPP_REG_LIST_DCN30_COMMON(id),\

}

#define dpp_regs_init(id)\

	DPP_REG_LIST_DCN30_COMMON_RI(id)



static const struct dcn3_dpp_registers dpp_regs[] = {

	dpp_regs(0),

	dpp_regs(1),

	dpp_regs(2),

	dpp_regs(3)

};

static struct dcn3_dpp_registers dpp_regs[4];



static const struct dcn3_dpp_shift tf_shift = {

		DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT)
@@ -466,17 +389,10 @@ static const struct dcn3_dpp_mask tf_mask = { 
};





#define opp_regs(id)\

[id] = {\

	OPP_REG_LIST_DCN30(id),\

}

#define opp_regs_init(id)\

	OPP_REG_LIST_DCN30_RI(id)



static const struct dcn20_opp_registers opp_regs[] = {

	opp_regs(0),

	opp_regs(1),

	opp_regs(2),

	opp_regs(3)

};

static struct dcn20_opp_registers opp_regs[4];



static const struct dcn20_opp_shift opp_shift = {

	OPP_MASK_SH_LIST_DCN20(__SHIFT)
@@ -486,21 +402,16 @@ static const struct dcn20_opp_mask opp_mask = { 
	OPP_MASK_SH_LIST_DCN20(_MASK)

};



#define aux_engine_regs(id)\

[id] = {\

	AUX_COMMON_REG_LIST0(id), \

	.AUXN_IMPCAL = 0, \

	.AUXP_IMPCAL = 0, \

	.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \

}

#define aux_engine_regs_init(id)\

	( \

	AUX_COMMON_REG_LIST0_RI(id), \

	SR_ARR_INIT(AUXN_IMPCAL, id, 0), \

	SR_ARR_INIT(AUXP_IMPCAL, id, 0), \

	SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \

	SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)\

	)



static const struct dce110_aux_registers aux_engine_regs[] = {

		aux_engine_regs(0),

		aux_engine_regs(1),

		aux_engine_regs(2),

		aux_engine_regs(3),

		aux_engine_regs(4)

};

static struct dce110_aux_registers aux_engine_regs[5];



static const struct dce110_aux_registers_shift aux_shift = {

	DCN_AUX_MASK_SH_LIST(__SHIFT)
@@ -510,15 +421,10 @@ static const struct dce110_aux_registers_mask aux_mask = { 
	DCN_AUX_MASK_SH_LIST(_MASK)

};



#define dwbc_regs_dcn3_init(id)\

	DWBC_COMMON_REG_LIST_DCN30_RI(id)



#define dwbc_regs_dcn3(id)\

[id] = {\

	DWBC_COMMON_REG_LIST_DCN30(id),\

}



static const struct dcn30_dwbc_registers dwbc30_regs[] = {

	dwbc_regs_dcn3(0),

};

static struct dcn30_dwbc_registers dwbc30_regs[1];



static const struct dcn30_dwbc_shift dwbc30_shift = {

	DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
@@ -528,14 +434,10 @@ static const struct dcn30_dwbc_mask dwbc30_mask = { 
	DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)

};



#define mcif_wb_regs_dcn3(id)\

[id] = {\

	MCIF_WB_COMMON_REG_LIST_DCN32(id),\

}

#define mcif_wb_regs_dcn3_init(id)\

	MCIF_WB_COMMON_REG_LIST_DCN32_RI(id)



static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {

	mcif_wb_regs_dcn3(0)

};

static struct dcn30_mmhubbub_registers mcif_wb30_regs[1];



static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {

	MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
@@ -545,17 +447,10 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 
	MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK)

};



#define dsc_regsDCN20(id)\

[id] = {\

	DSC_REG_LIST_DCN20(id)\

}

#define dsc_regsDCN20_init(id)\

	DSC_REG_LIST_DCN20_RI(id)



static const struct dcn20_dsc_registers dsc_regs[] = {

	dsc_regsDCN20(0),

	dsc_regsDCN20(1),

	dsc_regsDCN20(2),

	dsc_regsDCN20(3)

};

static struct dcn20_dsc_registers dsc_regs[4];



static const struct dcn20_dsc_shift dsc_shift = {

	DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
@@ -565,17 +460,23 @@ static const struct dcn20_dsc_mask dsc_mask = { 
	DSC_REG_LIST_SH_MASK_DCN20(_MASK)

};



static const struct dcn30_mpc_registers mpc_regs = {

		MPC_REG_LIST_DCN3_2(0),

		MPC_REG_LIST_DCN3_2(1),

		MPC_REG_LIST_DCN3_2(2),

		MPC_REG_LIST_DCN3_2(3),

		MPC_OUT_MUX_REG_LIST_DCN3_0(0),

		MPC_OUT_MUX_REG_LIST_DCN3_0(1),

		MPC_OUT_MUX_REG_LIST_DCN3_0(2),

		MPC_OUT_MUX_REG_LIST_DCN3_0(3),

		MPC_DWB_MUX_REG_LIST_DCN3_0(0),

};

static struct dcn30_mpc_registers mpc_regs;

#define dcn_mpc_regs_init()\

		( \

		MPC_REG_LIST_DCN3_0_RI(0),\

		MPC_REG_LIST_DCN3_0_RI(1),\

		MPC_REG_LIST_DCN3_0_RI(2),\

		MPC_REG_LIST_DCN3_0_RI(3),\

		MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\

		MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\

		MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\

		MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\

		MPC_MCM_REG_LIST_DCN32_RI(0),\

		MPC_MCM_REG_LIST_DCN32_RI(1),\

		MPC_MCM_REG_LIST_DCN32_RI(2),\

		MPC_MCM_REG_LIST_DCN32_RI(3),\

		MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)\

		)



static const struct dcn30_mpc_shift mpc_shift = {

	MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
@@ -585,19 +486,10 @@ static const struct dcn30_mpc_mask mpc_mask = { 
	MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)

};



#define optc_regs(id)\

[id] = {OPTC_COMMON_REG_LIST_DCN3_2(id)}



//#ifdef DIAGS_BUILD

//static struct dcn_optc_registers optc_regs[] = {

//#else

static const struct dcn_optc_registers optc_regs[] = {

//#endif

	optc_regs(0),

	optc_regs(1),

	optc_regs(2),

	optc_regs(3)

};

#define optc_regs_init(id)\

	OPTC_COMMON_REG_LIST_DCN3_2_RI(id)



static struct dcn_optc_registers optc_regs[4];



static const struct dcn_optc_shift optc_shift = {

	OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
@@ -607,17 +499,10 @@ static const struct dcn_optc_mask optc_mask = { 
	OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK)

};



#define hubp_regs(id)\

[id] = {\

	HUBP_REG_LIST_DCN32(id)\

}

#define hubp_regs_init(id)\

	HUBP_REG_LIST_DCN32_RI(id)



static const struct dcn_hubp2_registers hubp_regs[] = {

		hubp_regs(0),

		hubp_regs(1),

		hubp_regs(2),

		hubp_regs(3)

};

static struct dcn_hubp2_registers hubp_regs[4];





static const struct dcn_hubp2_shift hubp_shift = {
@@ -627,9 +512,10 @@ static const struct dcn_hubp2_shift hubp_shift = { 
static const struct dcn_hubp2_mask hubp_mask = {

		HUBP_MASK_SH_LIST_DCN32(_MASK)

};

static const struct dcn_hubbub_registers hubbub_reg = {

		HUBBUB_REG_LIST_DCN32(0)

};



static struct dcn_hubbub_registers hubbub_reg;

#define hubbub_reg_init()\

		HUBBUB_REG_LIST_DCN32_RI(0)



static const struct dcn_hubbub_shift hubbub_shift = {

		HUBBUB_MASK_SH_LIST_DCN32(__SHIFT)
@@ -639,9 +525,10 @@ static const struct dcn_hubbub_mask hubbub_mask = { 
		HUBBUB_MASK_SH_LIST_DCN32(_MASK)

};



static const struct dccg_registers dccg_regs = {

		DCCG_REG_LIST_DCN32()

};

static struct dccg_registers dccg_regs;



#define dccg_regs_init()\

	DCCG_REG_LIST_DCN32_RI()



static const struct dccg_shift dccg_shift = {

		DCCG_MASK_SH_LIST_DCN32(__SHIFT)
@@ -714,9 +601,10 @@ static const struct dccg_mask dccg_mask = { 
	SR(AZALIA_AUDIO_DTO), \

	SR(AZALIA_CONTROLLER_CLOCK_GATING)



static const struct dce_hwseq_registers hwseq_reg = {

static struct dce_hwseq_registers hwseq_reg;



#define hwseq_reg_init()\

	HWSEQ_DCN32_REG_LIST()

};



#define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\

	HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
@@ -759,29 +647,10 @@ static const struct dce_hwseq_shift hwseq_shift = { 
static const struct dce_hwseq_mask hwseq_mask = {

		HWSEQ_DCN32_MASK_SH_LIST(_MASK)

};

#define vmid_regs(id)\

[id] = {\

		DCN20_VMID_REG_LIST(id)\

}



static const struct dcn_vmid_registers vmid_regs[] = {

	vmid_regs(0),

	vmid_regs(1),

	vmid_regs(2),

	vmid_regs(3),

	vmid_regs(4),

	vmid_regs(5),

	vmid_regs(6),

	vmid_regs(7),

	vmid_regs(8),

	vmid_regs(9),

	vmid_regs(10),

	vmid_regs(11),

	vmid_regs(12),

	vmid_regs(13),

	vmid_regs(14),

	vmid_regs(15)

};

#define vmid_regs_init(id)\

		DCN20_VMID_REG_LIST_RI(id)



static struct dcn_vmid_registers vmid_regs[16];



static const struct dcn20_vmid_shift vmid_shifts = {

		DCN20_VMID_MASK_SH_LIST(__SHIFT)
@@ -903,6 +772,14 @@ static struct dce_aux *dcn32_aux_engine_create( 
	if (!aux_engine)

		return NULL;



#undef REG_STRUCT

#define REG_STRUCT aux_engine_regs

	aux_engine_regs_init(0),

	aux_engine_regs_init(1),

	aux_engine_regs_init(2),

	aux_engine_regs_init(3),

	aux_engine_regs_init(4);



	dce110_aux_engine_construct(aux_engine, ctx, inst,

				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,

				    &aux_engine_regs[inst],
@@ -912,15 +789,10 @@ static struct dce_aux *dcn32_aux_engine_create( 


	return &aux_engine->base;

}

#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }

#define i2c_inst_regs_init(id)\

	I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)



static const struct dce_i2c_registers i2c_hw_regs[] = {

		i2c_inst_regs(1),

		i2c_inst_regs(2),

		i2c_inst_regs(3),

		i2c_inst_regs(4),

		i2c_inst_regs(5),

};

static struct dce_i2c_registers i2c_hw_regs[6];



static const struct dce_i2c_shift i2c_shifts = {

		I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
@@ -940,6 +812,14 @@ static struct dce_i2c_hw *dcn32_i2c_hw_create( 
	if (!dce_i2c_hw)

		return NULL;



#undef REG_STRUCT

#define REG_STRUCT i2c_hw_regs

	i2c_inst_regs_init(1),

	i2c_inst_regs_init(2),

	i2c_inst_regs_init(3),

	i2c_inst_regs_init(4),

	i2c_inst_regs_init(5);



	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,

				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
@@ -979,6 +859,29 @@ static struct hubbub *dcn32_hubbub_create(struct dc_context *ctx) 
	if (!hubbub2)

		return NULL;



#undef REG_STRUCT

#define REG_STRUCT hubbub_reg

	hubbub_reg_init();



#undef REG_STRUCT

#define REG_STRUCT vmid_regs

	vmid_regs_init(0),

	vmid_regs_init(1),

	vmid_regs_init(2),

	vmid_regs_init(3),

	vmid_regs_init(4),

	vmid_regs_init(5),

	vmid_regs_init(6),

	vmid_regs_init(7),

	vmid_regs_init(8),

	vmid_regs_init(9),

	vmid_regs_init(10),

	vmid_regs_init(11),

	vmid_regs_init(12),

	vmid_regs_init(13),

	vmid_regs_init(14),

	vmid_regs_init(15);



	hubbub32_construct(hubbub2, ctx,

			&hubbub_reg,

			&hubbub_shift,
@@ -1011,6 +914,13 @@ static struct hubp *dcn32_hubp_create( 
	if (!hubp2)

		return NULL;



#undef REG_STRUCT

#define REG_STRUCT hubp_regs

		hubp_regs_init(0),

		hubp_regs_init(1),

		hubp_regs_init(2),

		hubp_regs_init(3);



	if (hubp32_construct(hubp2, ctx, inst,

			&hubp_regs[inst], &hubp_shift, &hubp_mask))

		return &hubp2->base;
@@ -1036,6 +946,13 @@ static struct dpp *dcn32_dpp_create( 
	if (!dpp3)

		return NULL;



#undef REG_STRUCT

#define REG_STRUCT dpp_regs

	dpp_regs_init(0),

	dpp_regs_init(1),

	dpp_regs_init(2),

	dpp_regs_init(3);



	if (dpp32_construct(dpp3, ctx, inst,

			&dpp_regs[inst], &tf_shift, &tf_mask))

		return &dpp3->base;
@@ -1056,6 +973,10 @@ static struct mpc *dcn32_mpc_create( 
	if (!mpc30)

		return NULL;



#undef REG_STRUCT

#define REG_STRUCT mpc_regs

	dcn_mpc_regs_init();



	dcn32_mpc_construct(mpc30, ctx,

			&mpc_regs,

			&mpc_shift,
@@ -1077,6 +998,13 @@ static struct output_pixel_processor *dcn32_opp_create( 
		return NULL;

	}



#undef REG_STRUCT

#define REG_STRUCT opp_regs

	opp_regs_init(0),

	opp_regs_init(1),

	opp_regs_init(2),

	opp_regs_init(3);



	dcn20_opp_construct(opp2, ctx, inst,

			&opp_regs[inst], &opp_shift, &opp_mask);

	return &opp2->base;
@@ -1093,6 +1021,13 @@ static struct timing_generator *dcn32_timing_generator_create( 
	if (!tgn10)

		return NULL;



#undef REG_STRUCT

#define REG_STRUCT optc_regs

	optc_regs_init(0),

	optc_regs_init(1),

	optc_regs_init(2),

	optc_regs_init(3);



	tgn10->base.inst = instance;

	tgn10->base.ctx = ctx;
@@ -1127,6 +1062,30 @@ static struct link_encoder *dcn32_link_encoder_create( 
	if (!enc20)

		return NULL;



#undef REG_STRUCT

#define REG_STRUCT link_enc_aux_regs

	aux_regs_init(0),

	aux_regs_init(1),

	aux_regs_init(2),

	aux_regs_init(3),

	aux_regs_init(4);



#undef REG_STRUCT

#define REG_STRUCT link_enc_hpd_regs

	hpd_regs_init(0),

	hpd_regs_init(1),

	hpd_regs_init(2),

	hpd_regs_init(3),

	hpd_regs_init(4);



#undef REG_STRUCT

#define REG_STRUCT link_enc_regs

	link_regs_init(0, A),

	link_regs_init(1, B),

	link_regs_init(2, C),

	link_regs_init(3, D),

	link_regs_init(4, E);



	dcn32_link_encoder_construct(enc20,

			enc_init_data,

			&link_enc_feature,
@@ -1156,7 +1115,7 @@ static void read_dce_straps( 
	struct dc_context *ctx,

	struct resource_straps *straps)

{

	generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),

	generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS,

		FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);



}
@@ -1164,6 +1123,15 @@ static void read_dce_straps( 
static struct audio *dcn32_create_audio(

		struct dc_context *ctx, unsigned int inst)

{



#undef REG_STRUCT

#define REG_STRUCT audio_regs

	audio_regs_init(0),

	audio_regs_init(1),

	audio_regs_init(2),

	audio_regs_init(3),

	audio_regs_init(4);



	return dce_audio_create(ctx, inst,

			&audio_regs[inst], &audio_shift, &audio_mask);

}
@@ -1177,6 +1145,19 @@ static struct vpg *dcn32_vpg_create( 
	if (!vpg3)

		return NULL;



#undef REG_STRUCT

#define REG_STRUCT vpg_regs

	vpg_regs_init(0),

	vpg_regs_init(1),

	vpg_regs_init(2),

	vpg_regs_init(3),

	vpg_regs_init(4),

	vpg_regs_init(5),

	vpg_regs_init(6),

	vpg_regs_init(7),

	vpg_regs_init(8),

	vpg_regs_init(9);



	vpg3_construct(vpg3, ctx, inst,

			&vpg_regs[inst],

			&vpg_shift,
@@ -1194,6 +1175,15 @@ static struct afmt *dcn32_afmt_create( 
	if (!afmt3)

		return NULL;



#undef REG_STRUCT

#define REG_STRUCT afmt_regs

	afmt_regs_init(0),

	afmt_regs_init(1),

	afmt_regs_init(2),

	afmt_regs_init(3),

	afmt_regs_init(4),

	afmt_regs_init(5);



	afmt3_construct(afmt3, ctx, inst,

			&afmt_regs[inst],

			&afmt_shift,
@@ -1211,6 +1201,13 @@ static struct apg *dcn31_apg_create( 
	if (!apg31)

		return NULL;



#undef REG_STRUCT

#define REG_STRUCT apg_regs

	apg_regs_init(0),

	apg_regs_init(1),

	apg_regs_init(2),

	apg_regs_init(3);



	apg31_construct(apg31, ctx, inst,

			&apg_regs[inst],

			&apg_shift,
@@ -1247,6 +1244,14 @@ static struct stream_encoder *dcn32_stream_encoder_create( 
		return NULL;

	}



#undef REG_STRUCT

#define REG_STRUCT stream_enc_regs

	stream_enc_regs_init(0),

	stream_enc_regs_init(1),

	stream_enc_regs_init(2),

	stream_enc_regs_init(3),

	stream_enc_regs_init(4);



	dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,

					eng_id, vpg, afmt,

					&stream_enc_regs[eng_id],
@@ -1297,6 +1302,13 @@ static struct hpo_dp_stream_encoder *dcn32_hpo_dp_stream_encoder_create( 
		return NULL;

	}



#undef REG_STRUCT

#define REG_STRUCT hpo_dp_stream_enc_regs

	hpo_dp_stream_encoder_reg_init(0),

	hpo_dp_stream_encoder_reg_init(1),

	hpo_dp_stream_encoder_reg_init(2),

	hpo_dp_stream_encoder_reg_init(3);



	dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,

					hpo_dp_inst, eng_id, vpg, apg,

					&hpo_dp_stream_enc_regs[hpo_dp_inst],
@@ -1314,6 +1326,11 @@ static struct hpo_dp_link_encoder *dcn32_hpo_dp_link_encoder_create( 
	/* allocate HPO link encoder */

	hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);



#undef REG_STRUCT

#define REG_STRUCT hpo_dp_link_enc_regs

	hpo_dp_link_encoder_reg_init(0),

	hpo_dp_link_encoder_reg_init(1);



	hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst,

					&hpo_dp_link_enc_regs[inst],

					&hpo_dp_le_shift, &hpo_dp_le_mask);
@@ -1326,6 +1343,10 @@ static struct dce_hwseq *dcn32_hwseq_create( 
{

	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);



#undef REG_STRUCT

#define REG_STRUCT hwseq_reg

	hwseq_reg_init();



	if (hws) {

		hws->ctx = ctx;

		hws->regs = &hwseq_reg;
@@ -1517,6 +1538,10 @@ static bool dcn32_dwbc_create(struct dc_context *ctx, struct resource_pool *pool 
			return false;

		}



#undef REG_STRUCT

#define REG_STRUCT dwbc30_regs

		dwbc_regs_dcn3_init(0);



		dcn30_dwbc_construct(dwbc30, ctx,

				&dwbc30_regs[i],

				&dwbc30_shift,
@@ -1542,6 +1567,10 @@ static bool dcn32_mmhubbub_create(struct dc_context *ctx, struct resource_pool * 
			return false;

		}



#undef REG_STRUCT

#define REG_STRUCT mcif_wb30_regs

		mcif_wb_regs_dcn3_init(0);



		dcn32_mmhubbub_construct(mcif_wb30, ctx,

				&mcif_wb30_regs[i],

				&mcif_wb30_shift,
@@ -1564,6 +1593,13 @@ static struct display_stream_compressor *dcn32_dsc_create( 
		return NULL;

	}



#undef REG_STRUCT

#define REG_STRUCT dsc_regs

	dsc_regsDCN20_init(0),

	dsc_regsDCN20_init(1),

	dsc_regsDCN20_init(2),

	dsc_regsDCN20_init(3);



	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);



	dsc->max_image_width = 6016;
@@ -2000,6 +2036,28 @@ static bool dcn32_resource_construct( 
	uint32_t pipe_fuses = 0;

	uint32_t num_pipes  = 4;



	#undef REG_STRUCT

	#define REG_STRUCT bios_regs

		bios_regs_init();



	#undef REG_STRUCT

	#define REG_STRUCT clk_src_regs

		clk_src_regs_init(0, A),

		clk_src_regs_init(1, B),

		clk_src_regs_init(2, C),

		clk_src_regs_init(3, D),

		clk_src_regs_init(4, E);

	#undef REG_STRUCT

	#define REG_STRUCT abm_regs

		abm_regs_init(0),

		abm_regs_init(1),

		abm_regs_init(2),

		abm_regs_init(3);



	#undef REG_STRUCT

	#define REG_STRUCT dccg_regs

		dccg_regs_init();



	DC_FP_START();



	ctx->dc_bios->regs = &bios_regs;

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h

+1080 −0

File changed.

Preview size limit exceeded, changes collapsed.