Commit f7b5115c authored by Mark Brown's avatar Mark Brown Committed by Will Deacon
Browse files

arm64/sysreg: Convert ID_AA64ISAR1_EL1 to automatic generation 



Automatically generate defines for ID_AA64ISAR1_EL1, using the definitions
in DDI0487H.a. No functional changes.

Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20220704170302.2609529-21-broonie@kernel.org


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent d1b60bed

arch/arm64/include/asm/sysreg.h

+0 −34
Original line number Diff line number Diff line
@@ -201,7 +201,6 @@ 
#define SYS_ID_AA64AFR0_EL1		sys_reg(3, 0, 0, 5, 4)

#define SYS_ID_AA64AFR1_EL1		sys_reg(3, 0, 0, 5, 5)



#define SYS_ID_AA64ISAR1_EL1		sys_reg(3, 0, 0, 6, 1)

#define SYS_ID_AA64ISAR2_EL1		sys_reg(3, 0, 0, 6, 2)



#define SYS_ID_AA64MMFR0_EL1		sys_reg(3, 0, 0, 7, 0)
@@ -700,39 +699,6 @@ 
/* Position the attr at the correct index */

#define MAIR_ATTRIDX(attr, idx)		((attr) << ((idx) * 8))



/* id_aa64isar1 */

#define ID_AA64ISAR1_EL1_I8MM_SHIFT		52

#define ID_AA64ISAR1_EL1_DGH_SHIFT		48

#define ID_AA64ISAR1_EL1_BF16_SHIFT		44

#define ID_AA64ISAR1_EL1_SPECRES_SHIFT		40

#define ID_AA64ISAR1_EL1_SB_SHIFT		36

#define ID_AA64ISAR1_EL1_FRINTTS_SHIFT		32

#define ID_AA64ISAR1_EL1_GPI_SHIFT		28

#define ID_AA64ISAR1_EL1_GPA_SHIFT		24

#define ID_AA64ISAR1_EL1_LRCPC_SHIFT		20

#define ID_AA64ISAR1_EL1_FCMA_SHIFT		16

#define ID_AA64ISAR1_EL1_JSCVT_SHIFT		12

#define ID_AA64ISAR1_EL1_API_SHIFT		8

#define ID_AA64ISAR1_EL1_APA_SHIFT		5

#define ID_AA64ISAR1_EL1_DPB_SHIFT		0



#define ID_AA64ISAR1_EL1_APA_NI			0x0

#define ID_AA64ISAR1_EL1_APA_PAuth		0x1

#define ID_AA64ISAR1_EL1_APA_ARCH_EPAC		0x2

#define ID_AA64ISAR1_EL1_APA_Pauth2		0x3

#define ID_AA64ISAR1_EL1_APA_FPAC		0x4

#define ID_AA64ISAR1_EL1_APA_FPACCOMBINE	0x5

#define ID_AA64ISAR1_EL1_API_NI			0x0

#define ID_AA64ISAR1_EL1_API_PAuth		0x1

#define ID_AA64ISAR1_EL1_API_EPAC		0x2

#define ID_AA64ISAR1_EL1_API_PAuth2		0x3

#define ID_AA64ISAR1_EL1_API_FPAC		0x4

#define ID_AA64ISAR1_EL1_API_FPACCOMBINE	0x5

#define ID_AA64ISAR1_EL1_GPA_NI			0x0

#define ID_AA64ISAR1_EL1_GPA_IMP		0x1

#define ID_AA64ISAR1_EL1_GPI_NI			0x0

#define ID_AA64ISAR1_EL1_GPI_IMP		0x1



/* id_aa64isar2 */

#define ID_AA64ISAR2_EL1_BC_SHIFT		28

#define ID_AA64ISAR2_EL1_APA3_SHIFT		12

arch/arm64/tools/sysreg

+83 −0
Original line number Diff line number Diff line
@@ -114,6 +114,89 @@ EndEnum 
Res0	3:0

EndSysreg



Sysreg	ID_AA64ISAR1_EL1	3	0	0	6	1

Enum	63:60	LS64

	0b0000	NI

	0b0001	LS64

	0b0010	LS64_V

	0b0011	LS64_ACCDATA

EndEnum

Enum	59:56	XS

	0b0000	NI

	0b0001	IMP

EndEnum

Enum	55:52	I8MM

	0b0000	NI

	0b0001	IMP

EndEnum

Enum	51:48	DGH

	0b0000	NI

	0b0001	IMP

EndEnum

Enum	47:44	BF16

	0b0000	NI

	0b0001	IMP

	0b0010	EBF16

EndEnum

Enum	43:40	SPECRES

	0b0000	NI

	0b0001	IMP

EndEnum

Enum	39:36	SB

	0b0000	NI

	0b0001	IMP

EndEnum

Enum	35:32	FRINTTS

	0b0000	NI

	0b0001	IMP

EndEnum

Enum	31:28	GPI

	0b0000	NI

	0b0001	IMP

EndEnum

Enum	27:24	GPA

	0b0000	NI

	0b0001	IMP

EndEnum

Enum	23:20	LRCPC

	0b0000	NI

	0b0001	IMP

	0b0010	LRCPC2

EndEnum

Enum	19:16	FCMA

	0b0000	NI

	0b0001	IMP

EndEnum

Enum	15:12	JSCVT

	0b0000	NI

	0b0001	IMP

EndEnum

Enum	11:8	API

	0b0000	NI

	0b0001	PAuth

	0b0010	EPAC

	0b0011	PAuth2

	0b0100	FPAC

	0b0101	FPACCOMBINE

EndEnum

Enum	7:4	APA

	0b0000	NI

	0b0001	PAuth

	0b0010	EPAC

	0b0011	PAuth2

	0b0100	FPAC

	0b0101	FPACCOMBINE

EndEnum

Enum	3:0	DPB

	0b0000	NI

	0b0001	IMP

	0b0010	DPB2

EndEnum

EndSysreg

	0b0001	IMP

EndEnum

EndSysreg



Sysreg	SCTLR_EL1	3	0	1	0	0

Field	63	TIDCP

Field	62	SPINMASK