Commit f77ab3f8 authored by Peiyang Wang's avatar Peiyang Wang Committed by Jiantao Xiao
Browse files

net: hns3: dump more reg info based on ras mod 

driver inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I9A3QT


CVE: NA

----------------------------------------------------------------------

Dump more reg info base on ras mod before reset, which is useful to
analyze the ras error.

Signed-off-by: default avatarPeiyang Wang <wangpeiyang1@huawei.com>
Signed-off-by: default avatarJiantao Xiao <xiaojiantao1@h-partners.com>
parent 72c40945

drivers/net/ethernet/hisilicon/hns3/hnae3.h

+4 −0
Original line number Diff line number Diff line
@@ -106,6 +106,7 @@ enum HNAE3_DEV_CAP_BITS { 
	HNAE3_DEV_SUPPORT_TM_FLUSH_B,

	HNAE3_DEV_SUPPORT_VF_FAULT_B,

	HNAE3_DEV_SUPPORT_NOTIFY_PKT_B,

	HNAE3_DEV_SUPPORT_ERR_MOD_GEN_REG_B,

};



#define hnae3_ae_dev_fd_supported(ae_dev) \
@@ -186,6 +187,9 @@ enum HNAE3_DEV_CAP_BITS { 
#define hnae3_ae_dev_notify_pkt_supported(ae_dev) \

	test_bit(HNAE3_DEV_SUPPORT_NOTIFY_PKT_B, (ae_dev)->caps)



#define hnae3_ae_dev_gen_reg_dfx_supported(hdev) \

	test_bit(HNAE3_DEV_SUPPORT_ERR_MOD_GEN_REG_B, (hdev)->ae_dev->caps)



enum HNAE3_PF_CAP_BITS {

	HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B = 0,

};

drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c

+1 −0
Original line number Diff line number Diff line
@@ -159,6 +159,7 @@ static const struct hclge_comm_caps_bit_map hclge_pf_cmd_caps[] = { 
	{HCLGE_COMM_CAP_TM_FLUSH_B, HNAE3_DEV_SUPPORT_TM_FLUSH_B},

	{HCLGE_COMM_CAP_VF_FAULT_B, HNAE3_DEV_SUPPORT_VF_FAULT_B},

	{HCLGE_COMM_CAP_NOTIFY_PKT_B, HNAE3_DEV_SUPPORT_NOTIFY_PKT_B},

	{HCLGE_COMM_CAP_ERR_MOD_GEN_REG_B, HNAE3_DEV_SUPPORT_ERR_MOD_GEN_REG_B},

};



static const struct hclge_comm_caps_bit_map hclge_vf_cmd_caps[] = {

drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h

+2 −0
Original line number Diff line number Diff line
@@ -91,6 +91,7 @@ enum hclge_opcode_type { 
	HCLGE_OPC_DFX_RCB_REG		= 0x004D,

	HCLGE_OPC_DFX_TQP_REG		= 0x004E,

	HCLGE_OPC_DFX_SSU_REG_2		= 0x004F,

	HCLGE_OPC_DFX_GEN_REG		= 0x7038,



	HCLGE_OPC_QUERY_DEV_SPECS	= 0x0050,

	HCLGE_OPC_GET_QUEUE_ERR_VF      = 0x0067,
@@ -374,6 +375,7 @@ enum HCLGE_COMM_CAP_BITS { 
	HCLGE_COMM_CAP_WOL_B = 28,

	HCLGE_COMM_CAP_NOTIFY_PKT_B = 29,

	HCLGE_COMM_CAP_TM_FLUSH_B = 31,

	HCLGE_COMM_CAP_ERR_MOD_GEN_REG_B = 32,

};



enum HCLGE_COMM_API_CAP_BITS {

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c

+2 −4
Original line number Diff line number Diff line
@@ -161,10 +161,8 @@ static int hclge_dbg_get_dfx_bd_num(struct hclge_dev *hdev, int offset, 
	return 0;

}



static int hclge_dbg_cmd_send(struct hclge_dev *hdev,

			      struct hclge_desc *desc_src,

			      int index, int bd_num,

			      enum hclge_opcode_type cmd)

int hclge_dbg_cmd_send(struct hclge_dev *hdev, struct hclge_desc *desc_src,

		       int index, int bd_num, enum hclge_opcode_type cmd)

{

	struct hclge_desc *desc = desc_src;

	int ret, i;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.h

+3 −0
Original line number Diff line number Diff line
@@ -766,4 +766,7 @@ struct hclge_dbg_vlan_cfg { 
	u8 pri_only2;

};



int hclge_dbg_cmd_send(struct hclge_dev *hdev, struct hclge_desc *desc_src,

		       int index, int bd_num, enum hclge_opcode_type cmd);



#endif