Commit f749448e authored by Fuad Tabba's avatar Fuad Tabba Committed by Will Deacon
Browse files

arm64: __clean_dcache_area_pop to take end parameter instead of size 



To be consistent with other functions with similar names and
functionality in cacheflush.h, cache.S, and cachetlb.rst, change
to specify the range in terms of start and end, as opposed to
start and size.

No functional change intended.

Reported-by: default avatarWill Deacon <will@kernel.org>
Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
Signed-off-by: default avatarFuad Tabba <tabba@google.com>
Reviewed-by: default avatarArd Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20210524083001.2586635-15-tabba@google.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 1f42faf1

arch/arm64/include/asm/cacheflush.h

+1 −1
Original line number Diff line number Diff line
@@ -61,7 +61,7 @@ extern void invalidate_icache_range(unsigned long start, unsigned long end); 
extern void __flush_dcache_area(unsigned long start, unsigned long end);

extern void __inval_dcache_area(unsigned long start, unsigned long end);

extern void __clean_dcache_area_poc(unsigned long start, unsigned long end);

extern void __clean_dcache_area_pop(void *addr, size_t len);

extern void __clean_dcache_area_pop(unsigned long start, unsigned long end);

extern void __clean_dcache_area_pou(void *addr, size_t len);

extern long __flush_cache_user_range(unsigned long start, unsigned long end);

extern void sync_icache_aliases(void *kaddr, unsigned long len);

arch/arm64/lib/uaccess_flushcache.c

+2 −2
Original line number Diff line number Diff line
@@ -15,7 +15,7 @@ void memcpy_flushcache(void *dst, const void *src, size_t cnt) 
	 * barrier to order the cache maintenance against the memcpy.

	 */

	memcpy(dst, src, cnt);

	__clean_dcache_area_pop(dst, cnt);

	__clean_dcache_area_pop((unsigned long)dst, (unsigned long)dst + cnt);

}

EXPORT_SYMBOL_GPL(memcpy_flushcache);
@@ -33,6 +33,6 @@ unsigned long __copy_user_flushcache(void *to, const void __user *from, 
	rc = raw_copy_from_user(to, from, n);



	/* See above */

	__clean_dcache_area_pop(to, n - rc);

	__clean_dcache_area_pop((unsigned long)to, (unsigned long)to + n - rc);

	return rc;

}

arch/arm64/mm/cache.S

+4 −5
Original line number Diff line number Diff line
@@ -194,16 +194,15 @@ SYM_FUNC_END_PI(__clean_dcache_area_poc) 
SYM_FUNC_END(__dma_clean_area)



/*

 *	__clean_dcache_area_pop(kaddr, size)

 *	__clean_dcache_area_pop(start, end)

 *

 * 	Ensure that any D-cache lines for the interval [kaddr, kaddr+size)

 * 	Ensure that any D-cache lines for the interval [start, end)

 * 	are cleaned to the PoP.

 *

 *	- kaddr   - kernel address

 *	- size    - size in question

 *	- start   - virtual start address of region

 *	- end     - virtual end address of region

 */

SYM_FUNC_START_PI(__clean_dcache_area_pop)

	add	x1, x0, x1

	alternative_if_not ARM64_HAS_DCPOP

	b	__clean_dcache_area_poc

	alternative_else_nop_endif

arch/arm64/mm/flush.c

+1 −1
Original line number Diff line number Diff line
@@ -84,7 +84,7 @@ void arch_wb_cache_pmem(void *addr, size_t size) 
{

	/* Ensure order against any prior non-cacheable writes */

	dmb(osh);

	__clean_dcache_area_pop(addr, size);

	__clean_dcache_area_pop((unsigned long)addr, (unsigned long)addr + size);

}

EXPORT_SYMBOL_GPL(arch_wb_cache_pmem);