Commit f733f119 authored Feb 25, 2023 by Xi Ruoyao Committed by Huacai Chen Feb 25, 2023

LoongArch: Use la.pcrel instead of la.abs when it's trivially possible



Let's start to kill la.abs in preparation for the subsequent support of
the PIE kernel.

BTW, Re-tab the indention in arch/loongarch/kernel/entry.S for alignment.

Signed-off-by: Xi Ruoyao <xry111@xry111.site>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>

parent 41596803

arch/loongarch/include/asm/stackframe.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -90,7 +90,7 @@
		.endm

		.macro set_saved_sp stackp temp temp2
		la.abs \temp, kernelsp
		la.pcrel \temp, kernelsp
		#ifdef CONFIG_SMP
		LONG_ADD \temp, \temp, u0
		#endif

arch/loongarch/include/asm/uaccess.h

+0 −1

Original line number	Diff line number	Diff line
		@@ -22,7 +22,6 @@
		extern u64 __ua_limit;

		#define __UA_ADDR ".dword"
		#define __UA_LA "la.abs"
		#define __UA_LIMIT __ua_limit

		/*

arch/loongarch/kernel/entry.S

+45 −45

Original line number	Diff line number	Diff line
		@@ -20,7 +20,7 @@
		.align 5
		SYM_FUNC_START(handle_syscall)
		csrrd t0, PERCPU_BASE_KS
		la.abs t1, kernelsp
		la.pcrel t1, kernelsp
		add.d t1, t1, t0
		move t2, sp
		ld.d sp, t1, 0

arch/loongarch/kernel/head.S

+1 −1

Original line number	Diff line number	Diff line
		@@ -117,7 +117,7 @@ SYM_CODE_START(smpboot_entry)
		li.w t0, 0x00 # FPE=0, SXE=0, ASXE=0, BTE=0
		csrwr t0, LOONGARCH_CSR_EUEN

		la.abs t0, cpuboot_data
		la.pcrel t0, cpuboot_data
		ld.d sp, t0, CPU_BOOT_STACK
		ld.d tp, t0, CPU_BOOT_TINFO

arch/loongarch/mm/tlbex.S

+1 −2

Original line number	Diff line number	Diff line
		@@ -24,8 +24,7 @@
		move a0, sp
		REG_S a2, sp, PT_BVADDR
		li.w a1, \write
		la.abs t0, do_page_fault
		jirl ra, t0, 0
		bl do_page_fault
		RESTORE_ALL_AND_RET
		SYM_FUNC_END(tlb_do_page_fault_\write)
		.endm