Commit f72387e1 authored by Mark Brown's avatar Mark Brown Committed by Jie Liu
Browse files

arm64/cpufeature: Detect PE support for FEAT_NMI 

kunpeng inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I90N2C
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/misc.git/commit/?h=arm64-nmi&id=12b82c9d5754e1e85573fc35d931a7337c9b9658



----------------------------------------------------------------------

Use of FEAT_NMI requires that all the PEs in the system and the GIC have
NMI support. This patch implements the PE part of that detection.

In order to avoid problematic interactions between real and pseudo NMIs
we disable the architected feature if the user has enabled pseudo NMIs
on the command line. If this is done on a system where support for the
architected feature is detected then a warning is printed during boot in
order to help users spot what is likely to be a misconfiguration.

In order to allow KVM to offer the feature to guests even if pseudo NMIs
are in use by the host we have a separate feature for the raw feature
which is used in KVM.

Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Signed-off-by: default avatarJie Liu <liujie375@h-partners.com>
parent 7c694a36

arch/arm64/include/asm/cpufeature.h

+6 −0
Original line number Diff line number Diff line
@@ -815,6 +815,12 @@ static __always_inline bool system_uses_irq_prio_masking(void) 
	       cpus_have_const_cap(ARM64_HAS_GIC_PRIO_MASKING);

}



static __always_inline bool system_uses_nmi(void)

{

	return IS_ENABLED(CONFIG_ARM64_NMI) &&

		cpus_have_const_cap(ARM64_USES_NMI);

}



static inline bool system_supports_mte(void)

{

	return IS_ENABLED(CONFIG_ARM64_MTE) &&

arch/arm64/kernel/cpufeature.c

+65 −1
Original line number Diff line number Diff line
@@ -86,6 +86,7 @@ 
#include <asm/mmu_context.h>

#include <asm/mpam.h>

#include <asm/mte.h>

#include <asm/nmi.h>

#include <asm/processor.h>

#include <asm/smp.h>

#include <asm/sysreg.h>
@@ -256,6 +257,7 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 
};



static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_NMI_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),

		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0),
@@ -2132,9 +2134,11 @@ static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 
}

#endif /* CONFIG_ARM64_E0PD */



#ifdef CONFIG_ARM64_PSEUDO_NMI

#if IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) || IS_ENABLED(CONFIG_ARM64_NMI)

static bool enable_pseudo_nmi;

#endif



#ifdef CONFIG_ARM64_PSEUDO_NMI

static int __init early_enable_pseudo_nmi(char *p)

{

	return kstrtobool(p, &enable_pseudo_nmi);
@@ -2184,6 +2188,41 @@ static bool has_gic_prio_relaxed_sync(const struct arm64_cpu_capabilities *entry 
}

#endif



#ifdef CONFIG_ARM64_NMI

static bool use_nmi(const struct arm64_cpu_capabilities *entry, int scope)

{

	if (!has_cpuid_feature(entry, scope))

		return false;



	/*

	 * Having both real and pseudo NMIs enabled simultaneously is

	 * likely to cause confusion.  Since pseudo NMIs must be

	 * enabled with an explicit command line option, if the user

	 * has set that option on a system with real NMIs for some

	 * reason assume they know what they're doing.

	 */

	if (IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && enable_pseudo_nmi) {

		pr_info("Pseudo NMI enabled, not using architected NMI\n");

		return false;

	}



	return true;

}



static void nmi_enable(const struct arm64_cpu_capabilities *__unused)

{

	/*

	 * Enable use of NMIs controlled by ALLINT, SPINTMASK should

	 * be clear by default but make it explicit that we are using

	 * this mode.  Ensure that ALLINT is clear first in order to

	 * avoid leaving things masked.

	 */

	_allint_clear();

	sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPINTMASK, SCTLR_EL1_NMI);

	isb();

}

#endif



#ifdef CONFIG_ARM64_BTI

static void bti_enable(const struct arm64_cpu_capabilities *__unused)

{
@@ -2781,6 +2820,31 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.matches = has_cpuid_feature,

		ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, EVT, IMP)

	},

#ifdef CONFIG_ARM64_NMI

	{

		.desc = "Non-maskable Interrupts present",

		.capability = ARM64_HAS_NMI,

		.type = ARM64_CPUCAP_BOOT_CPU_FEATURE,

		.sys_reg = SYS_ID_AA64PFR1_EL1,

		.sign = FTR_UNSIGNED,

		.field_pos = ID_AA64PFR1_EL1_NMI_SHIFT,

		.field_width = 4,

		.min_field_value = ID_AA64PFR1_EL1_NMI_IMP,

		.matches = has_cpuid_feature,

	},

	{

		.desc = "Non-maskable Interrupts enabled",

		.capability = ARM64_USES_NMI,

		.type = ARM64_CPUCAP_BOOT_CPU_FEATURE,

		.sys_reg = SYS_ID_AA64PFR1_EL1,

		.sign = FTR_UNSIGNED,

		.field_pos = ID_AA64PFR1_EL1_NMI_SHIFT,

		.field_width = 4,

		.min_field_value = ID_AA64PFR1_EL1_NMI_IMP,

		.matches = use_nmi,

		.cpu_enable = nmi_enable,

	},

#endif

#ifdef CONFIG_ARM64_MPAM

	{

		.desc = "Memory Partitioning And Monitoring",

arch/arm64/tools/cpucaps

+2 −0
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ HAS_LDAPR 
HAS_LSE_ATOMICS

HAS_MOPS

HAS_NESTED_VIRT

HAS_NMI

HAS_NO_FPSIMD

HAS_NO_HW_PREFETCH

HAS_PAN
@@ -69,6 +70,7 @@ SPECTRE_BHB 
SSBS

SVE

UNMAP_KERNEL_AT_EL0

USES_NMI

WORKAROUND_834220

WORKAROUND_843419

WORKAROUND_845719