Commit f70b88b9 authored by Wesley Chalmers's avatar Wesley Chalmers Committed by Alex Deucher
Browse files

drm/amd/display: Program OPP before ODM 



[WHY]
HW expects OPP to be configured before ODM is enabled.
Failure to do so can cause errors.

Reviewed-by: default avatarAric Cyr <Aric.Cyr@amd.com>
Acked-by: default avatarAlan Liu <HaoPing.Liu@amd.com>
Signed-off-by: default avatarWesley Chalmers <Wesley.Chalmers@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 863fa85e

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

+25 −24
Original line number Diff line number Diff line
@@ -1509,6 +1509,31 @@ static enum dc_status apply_single_controller_ctx_to_hw( 
	if (!pipe_ctx->stream->apply_seamless_boot_optimization && dc->config.use_pipe_ctx_sync_logic)

		check_syncd_pipes_for_disabled_master_pipe(dc, context, pipe_ctx->pipe_idx);



	pipe_ctx->stream_res.opp->funcs->opp_program_fmt(

		pipe_ctx->stream_res.opp,

		&stream->bit_depth_params,

		&stream->clamping);



	pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(

			pipe_ctx->stream_res.opp,

			COLOR_SPACE_YCBCR601,

			stream->timing.display_color_depth,

			stream->signal);



	while (odm_pipe) {

		odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion(

				odm_pipe->stream_res.opp,

				COLOR_SPACE_YCBCR601,

				stream->timing.display_color_depth,

				stream->signal);



		odm_pipe->stream_res.opp->funcs->opp_program_fmt(

				odm_pipe->stream_res.opp,

				&stream->bit_depth_params,

				&stream->clamping);

		odm_pipe = odm_pipe->next_odm_pipe;

	}



	/* DCN3.1 FPGA Workaround

	 * Need to enable HPO DP Stream Encoder before setting OTG master enable.

	 * To do so, move calling function enable_stream_timing to only be done AFTER calling
@@ -1548,30 +1573,6 @@ static enum dc_status apply_single_controller_ctx_to_hw( 
	if (dc_is_dp_signal(pipe_ctx->stream->signal))

		dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_OTG);



	pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(

			pipe_ctx->stream_res.opp,

			COLOR_SPACE_YCBCR601,

			stream->timing.display_color_depth,

			stream->signal);



	pipe_ctx->stream_res.opp->funcs->opp_program_fmt(

		pipe_ctx->stream_res.opp,

		&stream->bit_depth_params,

		&stream->clamping);

	while (odm_pipe) {

		odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion(

				odm_pipe->stream_res.opp,

				COLOR_SPACE_YCBCR601,

				stream->timing.display_color_depth,

				stream->signal);



		odm_pipe->stream_res.opp->funcs->opp_program_fmt(

				odm_pipe->stream_res.opp,

				&stream->bit_depth_params,

				&stream->clamping);

		odm_pipe = odm_pipe->next_odm_pipe;

	}



	if (!stream->dpms_off)

		core_link_enable_stream(context, pipe_ctx);