Unverified Commit f6f7d870 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'memory-controller-drv-6.1-2' of... 

Merge tag 'memory-controller-drv-6.1-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers

Memory controller drivers for v6.1, part 2

Improvements in Synopsys DesignWare Universal Multi-Protocol Memory
Controller Devicetree bindings.  The bindings are being split into
one related to Synopsys core and into quite different derivative Zynq
A05 DDR Memory Controller.  Extend the Synopsys bindings with additional
properties to match upcoming new device support (Baikal-T1 support).

* tag 'memory-controller-drv-6.1-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
  dt-bindings: memory: snps,dw-umctl2-ddrc: Extend schema with IRQs/resets/clocks props
  dt-bindings: memory: snps,dw-umctl2-ddrc: Replace opencoded numbers with macros
  dt-bindings: memory: snps,dw-umctl2-ddrc: Use more descriptive device name
  dt-bindings: memory: synopsys,ddrc-ecc: Detach Zynq DDRC controller support

Link: https://lore.kernel.org/r/20220926105023.119781-1-krzysztof.kozlowski@linaro.org


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents f8acc844 5514acb0

Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml

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# SPDX-License-Identifier: GPL-2.0-only

%YAML 1.2

---

$id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-ddrc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Synopsys DesignWare Universal Multi-Protocol Memory Controller



maintainers:

  - Krzysztof Kozlowski <krzk@kernel.org>

  - Manish Narani <manish.narani@xilinx.com>

  - Michal Simek <michal.simek@xilinx.com>



description: |

  Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of

  working with the memory devices supporting up to (LP)DDR4 protocol. It can

  be equipped with SEC/DEC ECC feature if DRAM data bus width is either

  16-bits or 32-bits or 64-bits wide.



  For instance the ZynqMP DDR controller is based on the DW uMCTL2 v2.40a

  controller. It has an optional SEC/DEC ECC support in 64- and 32-bits

  bus width configurations.



properties:

  compatible:

    oneOf:

      - deprecated: true

        description: Synopsys DW uMCTL2 DDR controller v3.80a

        const: snps,ddrc-3.80a

      - description: Synopsys DW uMCTL2 DDR controller

        const: snps,dw-umctl2-ddrc

      - description: Xilinx ZynqMP DDR controller v2.40a

        const: xlnx,zynqmp-ddrc-2.40a



  interrupts:

    description:

      DW uMCTL2 DDRC IP-core provides individual IRQ signal for each event":"

      ECC Corrected Error, ECC Uncorrected Error, ECC Address Protection,

      Scrubber-Done signal, DFI Parity/CRC Error. Some platforms may have the

      signals merged before they reach the IRQ controller or have some of them

      absent in case if the corresponding feature is unavailable/disabled.

    minItems: 1

    maxItems: 5



  interrupt-names:

    minItems: 1

    maxItems: 5

    oneOf:

      - description: Common ECC CE/UE/Scrubber/DFI Errors IRQ

        items:

          - const: ecc

      - description: Individual ECC CE/UE/Scrubber/DFI Errors IRQs

        items:

          enum: [ ecc_ce, ecc_ue, ecc_ap, ecc_sbr, dfi_e ]



  reg:

    maxItems: 1



  clocks:

    description:

      A standard set of the clock sources contains CSRs bus clock, AXI-ports

      reference clock, DDRC core clock, Scrubber standalone clock

      (synchronous to the DDRC clock).

    minItems: 1

    maxItems: 4



  clock-names:

    minItems: 1

    maxItems: 4

    items:

      enum: [ pclk, aclk, core, sbr ]



  resets:

    description:

      Each clock domain can have separate reset signal.

    minItems: 1

    maxItems: 4



  reset-names:

    minItems: 1

    maxItems: 4

    items:

      enum: [ prst, arst, core, sbr ]



required:

  - compatible

  - reg

  - interrupts



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    memory-controller@fd070000 {

      compatible = "xlnx,zynqmp-ddrc-2.40a";

      reg = <0xfd070000 0x30000>;



      interrupt-parent = <&gic>;

      interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;

      interrupt-names = "ecc";

    };

  - |

    #include <dt-bindings/interrupt-controller/irq.h>



    memory-controller@3d400000 {

      compatible = "snps,dw-umctl2-ddrc";

      reg = <0x3d400000 0x400000>;



      interrupts = <147 IRQ_TYPE_LEVEL_HIGH>, <148 IRQ_TYPE_LEVEL_HIGH>,

                   <149 IRQ_TYPE_LEVEL_HIGH>, <150 IRQ_TYPE_LEVEL_HIGH>;

      interrupt-names = "ecc_ce", "ecc_ue", "ecc_sbr", "dfi_e";



      clocks = <&pclk>, <&aclk>, <&core_clk>, <&sbr_clk>;

      clock-names = "pclk", "aclk", "core", "sbr";

    };

...

Documentation/devicetree/bindings/memory-controllers/synopsys,ddrc-ecc.yaml

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# SPDX-License-Identifier: GPL-2.0-only

%YAML 1.2

---

$id: http://devicetree.org/schemas/memory-controllers/synopsys,ddrc-ecc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Synopsys IntelliDDR Multi Protocol memory controller



maintainers:

  - Krzysztof Kozlowski <krzk@kernel.org>

  - Manish Narani <manish.narani@xilinx.com>

  - Michal Simek <michal.simek@xilinx.com>



description: |

  The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and

  32-bit bus width configurations.



  The Zynq DDR ECC controller has an optional ECC support in half-bus width

  (16-bit) configuration.



  These both ECC controllers correct single bit ECC errors and detect double bit

  ECC errors.



properties:

  compatible:

    enum:

      - snps,ddrc-3.80a

      - xlnx,zynq-ddrc-a05

      - xlnx,zynqmp-ddrc-2.40a



  interrupts:

    maxItems: 1



  reg:

    maxItems: 1



required:

  - compatible

  - reg



allOf:

  - if:

      properties:

        compatible:

          contains:

            enum:

              - snps,ddrc-3.80a

              - xlnx,zynqmp-ddrc-2.40a

    then:

      required:

        - interrupts

    else:

      properties:

        interrupts: false



additionalProperties: false



examples:

  - |

    memory-controller@f8006000 {

        compatible = "xlnx,zynq-ddrc-a05";

        reg = <0xf8006000 0x1000>;

    };



  - |

    axi {

        #address-cells = <2>;

        #size-cells = <2>;



        memory-controller@fd070000 {

            compatible = "xlnx,zynqmp-ddrc-2.40a";

            reg = <0x0 0xfd070000 0x0 0x30000>;

            interrupt-parent = <&gic>;

            interrupts = <0 112 4>;

        };

    };

Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/memory-controllers/xlnx,zynq-ddrc-a05.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Zynq A05 DDR Memory Controller



maintainers:

  - Krzysztof Kozlowski <krzk@kernel.org>

  - Manish Narani <manish.narani@xilinx.com>

  - Michal Simek <michal.simek@xilinx.com>



description:

  The Zynq DDR ECC controller has an optional ECC support in half-bus width

  (16-bit) configuration. It is cappable of correcting single bit ECC errors

  and detecting double bit ECC errors.



properties:

  compatible:

    const: xlnx,zynq-ddrc-a05



  reg:

    maxItems: 1



required:

  - compatible

  - reg



additionalProperties: false



examples:

  - |

    memory-controller@f8006000 {

      compatible = "xlnx,zynq-ddrc-a05";

      reg = <0xf8006000 0x1000>;

    };

...

MAINTAINERS

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@@ -3087,6 +3087,8 @@ W: http://wiki.xilinx.com 
T:	git https://github.com/Xilinx/linux-xlnx.git

F:	Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml

F:	Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml

F:	Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml

F:	Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml

F:	Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml

F:	arch/arm/mach-zynq/

F:	drivers/clocksource/timer-cadence-ttc.c