Commit f6f52047 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'x86_urgent_for_v6.1_rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 fixes from Borislav Petkov:

 - Add new Intel CPU models

 - Enforce that TDX guests are successfully loaded only on TDX hardware
   where virtualization exception (#VE) delivery on kernel memory is
   disabled because handling those in all possible cases is "essentially
   impossible"

 - Add the proper include to the syscall wrappers so that BTF can see
   the real pt_regs definition and not only the forward declaration

* tag 'x86_urgent_for_v6.1_rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/cpu: Add several Intel server CPU model numbers
  x86/tdx: Panic on bad configs that #VE on "private" memory access
  x86/tdx: Prepare for using "INFO" call for a second purpose
  x86/syscall: Include asm/ptrace.h in syscall_wrapper header
parents 35697d81 7beade0d

arch/x86/coco/tdx/tdx.c

+18 −7
Original line number Diff line number Diff line
@@ -34,6 +34,8 @@ 
#define VE_GET_PORT_NUM(e)	((e) >> 16)

#define VE_IS_IO_STRING(e)	((e) & BIT(4))



#define ATTR_SEPT_VE_DISABLE	BIT(28)



/*

 * Wrapper for standard use of __tdx_hypercall with no output aside from

 * return code.
@@ -98,10 +100,11 @@ static inline void tdx_module_call(u64 fn, u64 rcx, u64 rdx, u64 r8, u64 r9, 
		panic("TDCALL %lld failed (Buggy TDX module!)\n", fn);

}



static u64 get_cc_mask(void)

static void tdx_parse_tdinfo(u64 *cc_mask)

{

	struct tdx_module_output out;

	unsigned int gpa_width;

	u64 td_attr;



	/*

	 * TDINFO TDX module call is used to get the TD execution environment
@@ -109,19 +112,27 @@ static u64 get_cc_mask(void) 
	 * information, etc. More details about the ABI can be found in TDX

	 * Guest-Host-Communication Interface (GHCI), section 2.4.2 TDCALL

	 * [TDG.VP.INFO].

	 */

	tdx_module_call(TDX_GET_INFO, 0, 0, 0, 0, &out);



	/*

	 * The highest bit of a guest physical address is the "sharing" bit.

	 * Set it for shared pages and clear it for private pages.

	 *

	 * The GPA width that comes out of this call is critical. TDX guests

	 * can not meaningfully run without it.

	 */

	tdx_module_call(TDX_GET_INFO, 0, 0, 0, 0, &out);



	gpa_width = out.rcx & GENMASK(5, 0);

	*cc_mask = BIT_ULL(gpa_width - 1);



	/*

	 * The highest bit of a guest physical address is the "sharing" bit.

	 * Set it for shared pages and clear it for private pages.

	 * The kernel can not handle #VE's when accessing normal kernel

	 * memory.  Ensure that no #VE will be delivered for accesses to

	 * TD-private memory.  Only VMM-shared memory (MMIO) will #VE.

	 */

	return BIT_ULL(gpa_width - 1);

	td_attr = out.rdx;

	if (!(td_attr & ATTR_SEPT_VE_DISABLE))

		panic("TD misconfiguration: SEPT_VE_DISABLE attibute must be set.\n");

}



/*
@@ -758,7 +769,7 @@ void __init tdx_early_init(void) 
	setup_force_cpu_cap(X86_FEATURE_TDX_GUEST);



	cc_set_vendor(CC_VENDOR_INTEL);

	cc_mask = get_cc_mask();

	tdx_parse_tdinfo(&cc_mask);

	cc_set_mask(cc_mask);



	/*

arch/x86/include/asm/intel-family.h

+10 −1
Original line number Diff line number Diff line
@@ -107,6 +107,11 @@ 


#define INTEL_FAM6_SAPPHIRERAPIDS_X	0x8F	/* Golden Cove */



#define INTEL_FAM6_EMERALDRAPIDS_X	0xCF



#define INTEL_FAM6_GRANITERAPIDS_X	0xAD

#define INTEL_FAM6_GRANITERAPIDS_D	0xAE



#define INTEL_FAM6_ALDERLAKE		0x97	/* Golden Cove / Gracemont */

#define INTEL_FAM6_ALDERLAKE_L		0x9A	/* Golden Cove / Gracemont */

#define INTEL_FAM6_ALDERLAKE_N		0xBE
@@ -118,7 +123,7 @@ 
#define INTEL_FAM6_METEORLAKE		0xAC

#define INTEL_FAM6_METEORLAKE_L		0xAA



/* "Small Core" Processors (Atom) */

/* "Small Core" Processors (Atom/E-Core) */



#define INTEL_FAM6_ATOM_BONNELL		0x1C /* Diamondville, Pineview */

#define INTEL_FAM6_ATOM_BONNELL_MID	0x26 /* Silverthorne, Lincroft */
@@ -145,6 +150,10 @@ 
#define INTEL_FAM6_ATOM_TREMONT		0x96 /* Elkhart Lake */

#define INTEL_FAM6_ATOM_TREMONT_L	0x9C /* Jasper Lake */



#define INTEL_FAM6_SIERRAFOREST_X	0xAF



#define INTEL_FAM6_GRANDRIDGE		0xB6



/* Xeon Phi */



#define INTEL_FAM6_XEON_PHI_KNL		0x57 /* Knights Landing */

arch/x86/include/asm/syscall_wrapper.h

+1 −1
Original line number Diff line number Diff line
@@ -6,7 +6,7 @@ 
#ifndef _ASM_X86_SYSCALL_WRAPPER_H

#define _ASM_X86_SYSCALL_WRAPPER_H



struct pt_regs;

#include <asm/ptrace.h>



extern long __x64_sys_ni_syscall(const struct pt_regs *regs);

extern long __ia32_sys_ni_syscall(const struct pt_regs *regs);