Commit f6b044e4 authored by Imre Deak's avatar Imre Deak
Browse files

drm/i915/adl_p: Require a minimum of 8 tiles stride for DPT FBs 



The specification only requires DPT FB strides to be POT aligned, but
there seems to be also a minimum of 8 stride tile requirement. Scanning
out FBs with < 8 stride tiles will result in pipe faults (even though
the stride is POT aligned).

Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Acked-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarMika Kahola <mika.kahola@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210506161930.309688-10-imre.deak@intel.com
parent d3b4aa43

drivers/gpu/drm/i915/display/intel_fb.c

+5 −1
Original line number Diff line number Diff line
@@ -601,7 +601,11 @@ plane_view_dst_stride_tiles(const struct intel_framebuffer *fb, int color_plane, 
			    unsigned int pitch_tiles)

{

	if (intel_fb_needs_pot_stride_remap(fb))

		return roundup_pow_of_two(pitch_tiles);

		/*

		 * ADL_P, the only platform needing a POT stride has a minimum

		 * of 8 stride tiles.

		 */

		return roundup_pow_of_two(max(pitch_tiles, 8u));

	else

		return pitch_tiles;

}