Commit f6aa0d71 authored by Tilak Tangudu's avatar Tilak Tangudu Committed by John Harrison
Browse files

drm/i915: Add Wa_22011802037 force cs halt 



Prior to doing a reset, SW must ensure command streamer is stopped,
as a workaround, to eliminate a race condition in GPM flow.
Setting both the ring stop and prefetch disable bits, will cause the
command streamer to halt.

Signed-off-by: default avatarTilak Tangudu <tilak.tangudu@intel.com>
Reviewed-by: default avatarJohn Harrison <John.C.Harrison@Intel.com>
Signed-off-by: default avatarJohn Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220415224025.3693037-2-umesh.nerlige.ramappa@intel.com
parent bcfc713f

drivers/gpu/drm/i915/gt/intel_engine_cs.c

+9 −0
Original line number Diff line number Diff line
@@ -1278,6 +1278,15 @@ static int __intel_engine_stop_cs(struct intel_engine_cs *engine, 
	int err;



	intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));



	/*

	 * Wa_22011802037 : gen12, Prior to doing a reset, ensure CS is

	 * stopped, set ring stop bit and prefetch disable bit to halt CS

	 */

	if (GRAPHICS_VER(engine->i915) == 12)

		intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),

				      _MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE));



	err = __intel_wait_for_register_fw(engine->uncore, mode,

					   MODE_IDLE, MODE_IDLE,

					   fast_timeout_us,

drivers/gpu/drm/i915/gt/intel_engine_regs.h

+1 −0
Original line number Diff line number Diff line
@@ -181,6 +181,7 @@ 
#define   GFX_SURFACE_FAULT_ENABLE		(1 << 12)

#define   GFX_REPLAY_MODE			(1 << 11)

#define   GFX_PSMI_GRANULARITY			(1 << 10)

#define   GEN12_GFX_PREFETCH_DISABLE		REG_BIT(10)

#define   GFX_PPGTT_ENABLE			(1 << 9)

#define   GEN8_GFX_PPGTT_48B			(1 << 7)

#define   GFX_FORWARD_VBLANK_MASK		(3 << 5)