Commit f6a18f35 authored by Suzuki K Poulose's avatar Suzuki K Poulose Committed by Greg Kroah-Hartman
Browse files

coresight: etm4x: Handle access to TRCSSPCICRn 

TRCSSPCICR<n> is present only if all of the following are true:
	TRCIDR4.NUMSSCC > n.
	TRCIDR4.NUMPC > 0b0000 .
	TRCSSCSR<n>.PC == 0b1

Add a helper function to check all the conditions.

Link: https://lore.kernel.org/r/20210110224850.1880240-2-suzuki.poulose@arm.com


Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: default avatarMathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-4-mathieu.poirier@linaro.org


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent b8336ad9

drivers/hwtracing/coresight/coresight-etm4x-core.c

+24 −5
Original line number Diff line number Diff line
@@ -59,6 +59,22 @@ static u64 etm4_get_access_type(struct etmv4_config *config); 


static enum cpuhp_state hp_online;



/*

 * Check if TRCSSPCICRn(i) is implemented for a given instance.

 *

 * TRCSSPCICRn is implemented only if :

 *	TRCSSPCICR<n> is present only if all of the following are true:

 *		TRCIDR4.NUMSSCC > n.

 *		TRCIDR4.NUMPC > 0b0000 .

 *		TRCSSCSR<n>.PC == 0b1

 */

static inline bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n)

{

	return (n < drvdata->nr_ss_cmp) &&

	       drvdata->nr_pe &&

	       (drvdata->config.ss_status[n] & TRCSSCSRn_PC);

}



static void etm4_os_unlock(struct etmv4_drvdata *drvdata)

{

	/* Writing 0 to TRCOSLAR unlocks the trace registers */
@@ -270,6 +286,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) 
			       drvdata->base + TRCSSCCRn(i));

		writel_relaxed(config->ss_status[i],

			       drvdata->base + TRCSSCSRn(i));

		if (etm4x_sspcicrn_present(drvdata, i))

			writel_relaxed(config->ss_pe_cmp[i],

				       drvdata->base + TRCSSPCICRn(i));

	}
@@ -1324,6 +1341,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) 
	for (i = 0; i < drvdata->nr_ss_cmp; i++) {

		state->trcssccr[i] = readl(drvdata->base + TRCSSCCRn(i));

		state->trcsscsr[i] = readl(drvdata->base + TRCSSCSRn(i));

		if (etm4x_sspcicrn_present(drvdata, i))

			state->trcsspcicr[i] = readl(drvdata->base + TRCSSPCICRn(i));

	}
@@ -1440,6 +1458,7 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) 
			       drvdata->base + TRCSSCCRn(i));

		writel_relaxed(state->trcsscsr[i],

			       drvdata->base + TRCSSCSRn(i));

		if (etm4x_sspcicrn_present(drvdata, i))

			writel_relaxed(state->trcsspcicr[i],

				       drvdata->base + TRCSSPCICRn(i));

	}

drivers/hwtracing/coresight/coresight-etm4x.h

+2 −0
Original line number Diff line number Diff line
@@ -179,6 +179,8 @@ 
#define TRCSTATR_PMSTABLE_BIT		1

#define ETM_DEFAULT_ADDR_COMP		0



#define TRCSSCSRn_PC			BIT(3)



/* PowerDown Control Register bits */

#define TRCPDCR_PU			BIT(3)