Unverified Commit f655b9d0 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!5049 [OLK-6.6]Add pcie acs and no-bus-reset quirk for mucse Nics 

Merge Pull Request from: @guhuiguang 
 
1.Some MUCSE N10/N400 chips do not support bus/hot reset. The PCIE automatically disables LTSSM when Secondary Bus Reset is received and the device stops working. Prevent bus reset for these devices.

2.Some MUCSE N10/N400 chips may be multi-function devices, but the hardware does not advertise ACS capability. Add an ACS quirk for these chips NICS so the functions can be in independent IOMMU groups.

https://gitee.com/openeuler/kernel/issues/I96YCU
 
 
Link:https://gitee.com/openeuler/kernel/pulls/5049

 

Reviewed-by: default avatarJialin Zhang <zhangjialin11@huawei.com>
Reviewed-by: default avatarXiongfeng Wang <wangxiongfeng2@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parents e86cbfc1 bc518dae

drivers/pci/quirks.c

+47 −0
Original line number Diff line number Diff line
@@ -3768,6 +3768,32 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset); 
 */

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset);



/*

 * Some MUCSE N10/N400 chips do not support bus/hot reset.  The PCIESS

 * automatically disables LTSSM when Secondary Bus Reset is received and

 * the device stops working.  Prevent bus reset for these devices.

 */

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MUCSE, 0x1000, quirk_no_bus_reset);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MUCSE, 0x1c00, quirk_no_bus_reset);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MUCSE, 0x1004, quirk_no_bus_reset);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MUCSE, 0x1c04, quirk_no_bus_reset);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MUCSE, 0x1020, quirk_no_bus_reset);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MUCSE, 0x1c20, quirk_no_bus_reset);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MUCSE, 0x1060, quirk_no_bus_reset);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MUCSE, 0x1c60, quirk_no_bus_reset);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MUCSE, 0x1062, quirk_no_bus_reset);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MUCSE, 0x1c62, quirk_no_bus_reset);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MUCSE, 0x1001, quirk_no_bus_reset);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MUCSE, 0x1c01, quirk_no_bus_reset);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MUCSE, 0x1003, quirk_no_bus_reset);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MUCSE, 0x1c03, quirk_no_bus_reset);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MUCSE, 0x1021, quirk_no_bus_reset);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MUCSE, 0x1c21, quirk_no_bus_reset);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MUCSE, 0x1061, quirk_no_bus_reset);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MUCSE, 0x1c61, quirk_no_bus_reset);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MUCSE, 0x1083, quirk_no_bus_reset);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MUCSE, 0x1c83, quirk_no_bus_reset);



static void quirk_no_pm_reset(struct pci_dev *dev)

{

	/*
@@ -5147,6 +5173,27 @@ static const struct pci_dev_acs_enabled { 
	{ PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs },

	/* Wangxun nics */

	{ PCI_VENDOR_ID_WANGXUN, PCI_ANY_ID, pci_quirk_wangxun_nic_acs },

	/* Mucse multi-function devices */

	{ PCI_VENDOR_ID_MUCSE, 0x1000, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_MUCSE, 0x1c00, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_MUCSE, 0x1004, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_MUCSE, 0x1c04, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_MUCSE, 0x1020, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_MUCSE, 0x1c20, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_MUCSE, 0x1060, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_MUCSE, 0x1c60, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_MUCSE, 0x1062, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_MUCSE, 0x1c62, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_MUCSE, 0x1001, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_MUCSE, 0x1c01, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_MUCSE, 0x1003, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_MUCSE, 0x1c03, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_MUCSE, 0x1021, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_MUCSE, 0x1c21, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_MUCSE, 0x1061, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_MUCSE, 0x1c61, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_MUCSE, 0x1083, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_MUCSE, 0x1c83, pci_quirk_mf_endpoint_acs },

	{ 0 }

};

include/linux/pci_ids.h

+2 −0
Original line number Diff line number Diff line
@@ -3108,6 +3108,8 @@ 
#define PCI_DEVICE_ID_INTEL_HDA_CML_R	0xf0c8

#define PCI_DEVICE_ID_INTEL_HDA_RKL_S	0xf1c8



#define PCI_VENDOR_ID_MUCSE		0x8848



#define PCI_VENDOR_ID_WANGXUN		0x8088



#define PCI_VENDOR_ID_SCALEMP		0x8686