Commit f64668f9 authored by Likun Gao's avatar Likun Gao Committed by Alex Deucher
Browse files

drm/amdgpu: only use one gfx pipe for Sienna_Cichlid 



Only enable one gfx pipe for sienna_cichlid currently.

Signed-off-by: default avatarLikun Gao <Likun.Gao@amd.com>
Acked-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 338d90b6

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+2 −2
Original line number Diff line number Diff line
@@ -55,7 +55,7 @@ 
 * 2. Async ring

 */

#define GFX10_NUM_GFX_RINGS_NV1X	1

#define GFX10_NUM_GFX_RINGS_Sienna_Cichlid	2

#define GFX10_NUM_GFX_RINGS_Sienna_Cichlid	1

#define GFX10_MEC_HPD_SIZE	2048



#define F32_CE_PROGRAM_RAM_SIZE		65536
@@ -4232,7 +4232,7 @@ static int gfx_v10_0_sw_init(void *handle) 
		break;

	case CHIP_SIENNA_CICHLID:

		adev->gfx.me.num_me = 1;

		adev->gfx.me.num_pipe_per_me = 2;

		adev->gfx.me.num_pipe_per_me = 1;

		adev->gfx.me.num_queue_per_pipe = 1;

		adev->gfx.mec.num_mec = 2;

		adev->gfx.mec.num_pipe_per_mec = 4;