Commit f64234fa authored by Amit Daniel Kachhap's avatar Amit Daniel Kachhap Committed by Catalin Marinas
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arm64: Add compat hwcap ASIMDBF16 



This hwcap was added earlier for 32-bit native arm kernel by commit
23b6d4ad ("ARM: 9271/1: vfp: Add hwcap for FEAT_AA32BF16") and hence
the corresponding changes added in 32-bit compat arm64 kernel.

Brain 16-bit floating-point storage format is a feature (FEAT_AA32BF16)
present in AArch32 state for Armv8 and is represented by ISAR6.BF16
identification register. Similar feature (FEAT_BF16) exist for AArch64
state and is already advertised in native arm64 kernel.

Signed-off-by: default avatarAmit Daniel Kachhap <amit.kachhap@arm.com>
Reviewed-by: default avatarMark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20230111053706.13994-5-amit.kachhap@arm.com


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 4a87be25

arch/arm64/include/asm/hwcap.h

+1 −0
Original line number Diff line number Diff line
@@ -35,6 +35,7 @@ 
#define COMPAT_HWCAP_ASIMDHP	(1 << 23)

#define COMPAT_HWCAP_ASIMDDP	(1 << 24)

#define COMPAT_HWCAP_ASIMDFHM	(1 << 25)

#define COMPAT_HWCAP_ASIMDBF16	(1 << 26)



#define COMPAT_HWCAP2_AES	(1 << 0)

#define COMPAT_HWCAP2_PMULL	(1 << 1)

arch/arm64/kernel/cpufeature.c

+2 −1
Original line number Diff line number Diff line
@@ -530,7 +530,7 @@ static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 


static const struct arm64_ftr_bits ftr_id_isar6[] = {

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_I8MM_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_BF16_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_BF16_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SPECRES_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SB_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_FHM_SHIFT, 4, 0),
@@ -2875,6 +2875,7 @@ static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 
	HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_EL1_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),

	HWCAP_CAP(SYS_ID_ISAR6_EL1, ID_ISAR6_EL1_DP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP),

	HWCAP_CAP(SYS_ID_ISAR6_EL1, ID_ISAR6_EL1_FHM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM),

	HWCAP_CAP(SYS_ID_ISAR6_EL1, ID_ISAR6_EL1_BF16_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16),

#endif

	{},

};

arch/arm64/kernel/cpuinfo.c

+1 −0
Original line number Diff line number Diff line
@@ -150,6 +150,7 @@ static const char *const compat_hwcap_str[] = { 
	[COMPAT_KERNEL_HWCAP(ASIMDHP)]	= "asimdhp",

	[COMPAT_KERNEL_HWCAP(ASIMDDP)]	= "asimddp",

	[COMPAT_KERNEL_HWCAP(ASIMDFHM)]	= "asimdfhm",

	[COMPAT_KERNEL_HWCAP(ASIMDBF16)] = "asimdbf16",

};



#define COMPAT_KERNEL_HWCAP2(x)	const_ilog2(COMPAT_HWCAP2_ ## x)