Commit f638e7fd authored by Stefan Riedmueller's avatar Stefan Riedmueller Committed by Shawn Guo
Browse files

ARM: dts: imx6ul: segin: Move ECSPI interface to board include file 



The ECSPI interface is available on the expansion connector of every
PHYTEC phyBOARD-Segin. Move its definition to the board include file
for better reuse.

Signed-off-by: default avatarStefan Riedmueller <s.riedmueller@phytec.de>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent b349580a

arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts

+0 −14
Original line number Diff line number Diff line
@@ -28,9 +28,6 @@ 
};



&ecspi3 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_ecspi3>;

	cs-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;

	status = "okay";

};
@@ -93,14 +90,3 @@ 
&usdhc1 {

	status = "okay";

};
 


&iomuxc {

	pinctrl_ecspi3: ecspi3grp {

		fsl,pins = <

			MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO	0x10b0

			MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI	0x10b0

			MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK	0x10b0

			MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20	0x10b0

		>;

	};

};

arch/arm/boot/dts/imx6ul-phytec-segin.dtsi

+16 −0
Original line number Diff line number Diff line
@@ -103,6 +103,13 @@ 
	assigned-clock-rates = <786432000>;

};



&ecspi3 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_ecspi3>;

	cs-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;

	status = "disabled";

};



&fec2 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_enet2>;
@@ -225,6 +232,15 @@ 
		>;

	};



	pinctrl_ecspi3: ecspi3grp {

		fsl,pins = <

			MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO	0x10b0

			MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI	0x10b0

			MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK	0x10b0

			MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20	0x10b0

		>;

	};



	pinctrl_enet2: enet2grp {

		fsl,pins = <

			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0