Unverified Commit f627476e authored by Palmer Dabbelt's avatar Palmer Dabbelt
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RISC-V: Use asm-generic for {in,out}{bwlq} 



The asm-generic implementation is functionally identical to the RISC-V
version.

Signed-off-by: default avatarPalmer Dabbelt <palmerdabbelt@google.com>
Reviewed-by: default avatarAnup Patel <anup@brainfault.org>
Signed-off-by: default avatarPalmer Dabbelt <palmerdabbelt@google.com>
parent 3f1e7829

arch/riscv/include/asm/io.h

+0 −13
Original line number Diff line number Diff line
@@ -52,19 +52,6 @@ 
#define __io_pbw()	__asm__ __volatile__ ("fence iow,o" : : : "memory");

#define __io_paw()	__asm__ __volatile__ ("fence o,io"  : : : "memory");



#define inb(c)		({ u8  __v; __io_pbr(); __v = readb_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; })

#define inw(c)		({ u16 __v; __io_pbr(); __v = readw_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; })

#define inl(c)		({ u32 __v; __io_pbr(); __v = readl_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; })



#define outb(v,c)	({ __io_pbw(); writeb_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); })

#define outw(v,c)	({ __io_pbw(); writew_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); })

#define outl(v,c)	({ __io_pbw(); writel_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); })



#ifdef CONFIG_64BIT

#define inq(c)		({ u64 __v; __io_pbr(); __v = readq_cpu((void*)(c)); __io_par(__v); __v; })

#define outq(v,c)	({ __io_pbw(); writeq_cpu((v),(void*)(c)); __io_paw(); })

#endif



/*

 * Accesses from a single hart to a single I/O address must be ordered.  This

 * allows us to use the raw read macros, but we still need to fence before and