Commit f60500f3 authored by Arun R Murthy's avatar Arun R Murthy Committed by Jani Nikula
Browse files

drm/i915/display/dp: 128/132b LT requirement 



For 128b/132b LT prior to LT DPTX should set power state, DP channel
coding and then link rate.

v2: added separate function to avoid code duplication(Jani N)
v3: DP2.1 section 3.5.2.16 is ordered, 3.5.1.2 is unordered and hence
    discarding <Ville>

Signed-off-by: default avatarArun R Murthy <arun.r.murthy@intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230425025944.151744-1-arun.r.murthy@intel.com
parent ee963428

drivers/gpu/drm/i915/display/intel_dp_link_training.c

+39 −18
Original line number Diff line number Diff line
@@ -637,6 +637,38 @@ static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp, 
	return true;

}



static void

intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,

				const struct intel_crtc_state *crtc_state)

{

	u8 link_config[2];



	link_config[0] = crtc_state->vrr.flipline ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;

	link_config[1] = intel_dp_is_uhbr(crtc_state) ?

			 DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;

	drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);

}



static void

intel_dp_update_link_bw_set(struct intel_dp *intel_dp,

			    const struct intel_crtc_state *crtc_state,

			    u8 link_bw, u8 rate_select)

{

	u8 link_config[2];



	/* Write the link configuration data */

	link_config[0] = link_bw;

	link_config[1] = crtc_state->lane_count;

	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))

		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;

	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);



	/* eDP 1.4 rate select method. */

	if (!link_bw)

		drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,

				  &rate_select, 1);

}



/*

 * Prepare link training by configuring the link parameters. On DDI platforms

 * also enable the port here.
@@ -647,7 +679,6 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp, 
{

	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

	struct drm_i915_private *i915 = to_i915(encoder->base.dev);

	u8 link_config[2];

	u8 link_bw, rate_select;



	if (intel_dp->prepare_link_retrain)
@@ -686,23 +717,13 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp, 
		drm_dbg_kms(&i915->drm,

			    "[ENCODER:%d:%s] Using LINK_RATE_SET value %02x\n",

			    encoder->base.base.id, encoder->base.name, rate_select);



	/* Write the link configuration data */

	link_config[0] = link_bw;

	link_config[1] = crtc_state->lane_count;

	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))

		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;

	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);



	/* eDP 1.4 rate select method. */

	if (!link_bw)

		drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,

				  &rate_select, 1);



	link_config[0] = crtc_state->vrr.flipline ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;

	link_config[1] = intel_dp_is_uhbr(crtc_state) ?

		DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;

	drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);

	/*

	 * Spec DP2.1 Section 3.5.2.16

	 * Prior to LT DPTX should set 128b/132b DP Channel coding and then set link rate

	 */

	intel_dp_update_downspread_ctrl(intel_dp, crtc_state);

	intel_dp_update_link_bw_set(intel_dp, crtc_state, link_bw,

				    rate_select);



	return true;

}