Commit f5e81d11 authored by Daniel Borkmann's avatar Daniel Borkmann
Browse files

bpf: Introduce BPF nospec instruction for mitigating Spectre v4 



In case of JITs, each of the JIT backends compiles the BPF nospec instruction
/either/ to a machine instruction which emits a speculation barrier /or/ to
/no/ machine instruction in case the underlying architecture is not affected
by Speculative Store Bypass or has different mitigations in place already.

This covers both x86 and (implicitly) arm64: In case of x86, we use 'lfence'
instruction for mitigation. In case of arm64, we rely on the firmware mitigation
as controlled via the ssbd kernel parameter. Whenever the mitigation is enabled,
it works for all of the kernel code with no need to provide any additional
instructions here (hence only comment in arm64 JIT). Other archs can follow
as needed. The BPF nospec instruction is specifically targeting Spectre v4
since i) we don't use a serialization barrier for the Spectre v1 case, and
ii) mitigation instructions for v1 and v4 might be different on some archs.

The BPF nospec is required for a future commit, where the BPF verifier does
annotate intermediate BPF programs with speculation barriers.

Co-developed-by: default avatarPiotr Krysiuk <piotras@gmail.com>
Co-developed-by: default avatarBenedict Schlueter <benedict.schlueter@rub.de>
Signed-off-by: default avatarDaniel Borkmann <daniel@iogearbox.net>
Signed-off-by: default avatarPiotr Krysiuk <piotras@gmail.com>
Signed-off-by: default avatarBenedict Schlueter <benedict.schlueter@rub.de>
Acked-by: default avatarAlexei Starovoitov <ast@kernel.org>
parent f1fdee33

arch/arm/net/bpf_jit_32.c

+3 −0
Original line number Diff line number Diff line
@@ -1602,6 +1602,9 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx) 
		rn = arm_bpf_get_reg32(src_lo, tmp2[1], ctx);

		emit_ldx_r(dst, rn, off, ctx, BPF_SIZE(code));

		break;

	/* speculation barrier */

	case BPF_ST | BPF_NOSPEC:

		break;

	/* ST: *(size *)(dst + off) = imm */

	case BPF_ST | BPF_MEM | BPF_W:

	case BPF_ST | BPF_MEM | BPF_H:

arch/arm64/net/bpf_jit_comp.c

+13 −0
Original line number Diff line number Diff line
@@ -823,6 +823,19 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx, 
			return ret;

		break;



	/* speculation barrier */

	case BPF_ST | BPF_NOSPEC:

		/*

		 * Nothing required here.

		 *

		 * In case of arm64, we rely on the firmware mitigation of

		 * Speculative Store Bypass as controlled via the ssbd kernel

		 * parameter. Whenever the mitigation is enabled, it works

		 * for all of the kernel code with no need to provide any

		 * additional instructions.

		 */

		break;



	/* ST: *(size *)(dst + off) = imm */

	case BPF_ST | BPF_MEM | BPF_W:

	case BPF_ST | BPF_MEM | BPF_H:

arch/mips/net/ebpf_jit.c

+3 −0
Original line number Diff line number Diff line
@@ -1355,6 +1355,9 @@ static int build_one_insn(const struct bpf_insn *insn, struct jit_ctx *ctx, 
		}

		break;



	case BPF_ST | BPF_NOSPEC: /* speculation barrier */

		break;



	case BPF_ST | BPF_B | BPF_MEM:

	case BPF_ST | BPF_H | BPF_MEM:

	case BPF_ST | BPF_W | BPF_MEM:

arch/powerpc/net/bpf_jit_comp32.c

+6 −0
Original line number Diff line number Diff line
@@ -737,6 +737,12 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context * 
			}

			break;



		/*

		 * BPF_ST NOSPEC (speculation barrier)

		 */

		case BPF_ST | BPF_NOSPEC:

			break;



		/*

		 * BPF_ST(X)

		 */

arch/powerpc/net/bpf_jit_comp64.c

+6 −0
Original line number Diff line number Diff line
@@ -627,6 +627,12 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context * 
			}

			break;



		/*

		 * BPF_ST NOSPEC (speculation barrier)

		 */

		case BPF_ST | BPF_NOSPEC:

			break;



		/*

		 * BPF_ST(X)

		 */